Unverified Commit 3eb8e5e6 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!161 SPR: IPI Virtualization Support 

Merge Pull Request from: @x56Jason 
 
This PR is to enable IPI virtualization support for Intel SPR, meanwhile fix kabi changes.

## Intel-Kernel Issue
#I5ODSC

## Test

1, build and boot succeed with CONFIG_SMP enabled or disabled.
2, Use IPI benchmark (https://lore.kernel.org/kvm/20171219085010.4081-1-ynorov@caviumnetworks.com) to do unicast IPI testing ("Normal IPI" case in the benchmark):
 - With host disabled IPI virtualization, and guest enable x2apic mode, we can see a lot of MSR_WR_VMEXITs
 - With host enabled IPI virtualization, and guest enable x2apic mode, MSR_WR_VMEXITs caused by IPI disappears.

## Known Issue
N/A

## Default Config Change
N/A
 
 
Link:https://gitee.com/openeuler/kernel/pulls/161

 
Reviewed-by: default avatarChen Wei <chenwei@xfusion.com>
Reviewed-by: default avatarKevin Zhu <zhukeqian1@huawei.com>
Signed-off-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
parents 0d3b47a1 f0af26c8

Documentation/virt/kvm/api.rst

+21 −0
Original line number Diff line number Diff line
@@ -6220,6 +6220,27 @@ default. 


See Documentation/x86/sgx.rst for more details.



7.23 KVM_CAP_MAX_VCPU_ID

------------------------



:Architectures: x86

:Target: VM

:Parameters: args[0] - maximum APIC ID value set for current VM

:Returns: 0 on success, -EINVAL if args[0] is beyond KVM_MAX_VCPU_ID

          supported in KVM or if it has been set.



This capability allows userspace to specify maximum possible APIC ID

assigned for current VM session prior to the creation of vCPUs, saving

memory for data structures indexed by the APIC ID.  Userspace is able

to calculate the limit to APIC ID values from designated

CPU topology.



The value can be changed only until KVM_ENABLE_CAP is set to a nonzero

value or until a vCPU is created.  Upon creation of the first vCPU,

if the value was set to zero or KVM_ENABLE_CAP was not invoked, KVM

uses the return value of KVM_CHECK_EXTENSION(KVM_CAP_MAX_VCPU_ID) as

the maximum APIC ID.



8. Other capabilities.

======================

arch/s390/kvm/kvm-s390.c

+0 −2
Original line number Diff line number Diff line
@@ -2944,9 +2944,7 @@ static int sca_can_add_vcpu(struct kvm *kvm, unsigned int id) 
	if (!sclp.has_esca || !sclp.has_64bscao)

		return false;



	mutex_lock(&kvm->lock);

	rc = kvm->arch.use_esca ? 0 : sca_switch_to_extended(kvm);

	mutex_unlock(&kvm->lock);



	return rc == 0 && id < KVM_S390_ESCA_CPU_SLOTS;

}

arch/x86/include/asm/kvm_host.h

+7 −0
Original line number Diff line number Diff line
@@ -1020,6 +1020,12 @@ struct kvm_arch { 
	struct list_head tdp_mmu_roots;

	/* List of struct tdp_mmu_pages not being used as roots */

	struct list_head tdp_mmu_pages;

	/*

	 * VM-scope maximum vCPU ID. Used to determine the size of structures

	 * that increase along with the maximum vCPU ID, in which case, using

	 * the global KVM_MAX_VCPU_ID may lead to significant memory waste.

	 */

	u32 max_vcpu_ids;

};



struct kvm_vm_stat {
@@ -1121,6 +1127,7 @@ struct kvm_x86_ops { 
	void (*vm_destroy)(struct kvm *kvm);



	/* Create, but do not attach this VCPU */

	int (*vcpu_precreate)(struct kvm *kvm);

	int (*vcpu_create)(struct kvm_vcpu *vcpu);

	void (*vcpu_free)(struct kvm_vcpu *vcpu);

	void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event);

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -956,6 +956,7 @@ 
#define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f

#define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490

#define MSR_IA32_VMX_VMFUNC             0x00000491

#define MSR_IA32_VMX_PROCBASED_CTLS3	0x00000492



/* VMX_BASIC bits and bitmasks */

#define VMX_BASIC_VMCS_SIZE_SHIFT	32

arch/x86/include/asm/processor.h

+16 −0
Original line number Diff line number Diff line
@@ -142,6 +142,12 @@ struct cpuinfo_x86 { 
	unsigned		initialized : 1;

} __randomize_layout;



struct extra_cpuinfo_x86 {

#ifdef CONFIG_X86_VMX_FEATURE_NAMES

	__u32			vmx_tertiary_capability[NVMX_TERTIARY_INTS];

#endif

} __randomize_layout;



struct cpuid_regs {

	u32 eax, ebx, ecx, edx;

};
@@ -172,6 +178,8 @@ enum cpuid_regs_idx { 
extern struct cpuinfo_x86	boot_cpu_data;

extern struct cpuinfo_x86	new_cpu_data;



extern struct extra_cpuinfo_x86	extra_boot_cpu_data;



extern __u32			cpu_caps_cleared[NCAPINTS + NBUGINTS];

extern __u32			cpu_caps_set[NCAPINTS + NBUGINTS];
@@ -183,6 +191,14 @@ DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 
#define cpu_data(cpu)		boot_cpu_data

#endif



#ifdef CONFIG_SMP

DECLARE_PER_CPU_READ_MOSTLY(struct extra_cpuinfo_x86, extra_cpu_info);

#define extra_cpu_data(cpu)	per_cpu(extra_cpu_info, cpu)

#else

#define extra_cpu_info		extra_boot_cpu_data

#define extra_cpu_data(cpu)	extra_boot_cpu_data

#endif



extern const struct seq_operations cpuinfo_op;



#define cache_line_size()	(boot_cpu_data.x86_cache_alignment)