Commit 3e6670a2 authored by Xingyu Wu's avatar Xingyu Wu Committed by Conor Dooley
Browse files

riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node 



Add PLL clocks input from PLL clocks driver in SYSCRG node.

Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 3fcbcfc4

arch/riscv/boot/dts/starfive/jh7110.dtsi

+6 −2
Original line number Diff line number Diff line
@@ -517,12 +517,16 @@ 
				 <&gmac1_rgmii_rxin>,

				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,

				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,

				 <&tdm_ext>, <&mclk_ext>;

				 <&tdm_ext>, <&mclk_ext>,

				 <&pllclk JH7110_PLLCLK_PLL0_OUT>,

				 <&pllclk JH7110_PLLCLK_PLL1_OUT>,

				 <&pllclk JH7110_PLLCLK_PLL2_OUT>;

			clock-names = "osc", "gmac1_rmii_refin",

				      "gmac1_rgmii_rxin",

				      "i2stx_bclk_ext", "i2stx_lrck_ext",

				      "i2srx_bclk_ext", "i2srx_lrck_ext",

				      "tdm_ext", "mclk_ext";

				      "tdm_ext", "mclk_ext",

				      "pll0_out", "pll1_out", "pll2_out";

			#clock-cells = <1>;

			#reset-cells = <1>;

		};