Commit 3fcbcfc4 authored by William Qiu's avatar William Qiu Committed by Conor Dooley
Browse files

riscv: dts: starfive: jh7110: Add syscon nodes 



Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 SoC.

Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Co-developed-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: default avatarWilliam Qiu <william.qiu@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 3d90131f

arch/riscv/boot/dts/starfive/jh7110.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -418,6 +418,11 @@ 
			#reset-cells = <1>;

		};



		stg_syscon: syscon@10240000 {

			compatible = "starfive,jh7110-stg-syscon", "syscon";

			reg = <0x0 0x10240000 0x0 0x1000>;

		};



		uart3: serial@12000000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x0 0x12000000 0x0 0x10000>;
@@ -522,6 +527,17 @@ 
			#reset-cells = <1>;

		};



		sys_syscon: syscon@13030000 {

			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";

			reg = <0x0 0x13030000 0x0 0x1000>;



			pllclk: clock-controller {

				compatible = "starfive,jh7110-pll";

				clocks = <&osc>;

				#clock-cells = <1>;

			};

		};



		sysgpio: pinctrl@13040000 {

			compatible = "starfive,jh7110-sys-pinctrl";

			reg = <0x0 0x13040000 0x0 0x10000>;
@@ -561,6 +577,12 @@ 
			#reset-cells = <1>;

		};



		aon_syscon: syscon@17010000 {

			compatible = "starfive,jh7110-aon-syscon", "syscon";

			reg = <0x0 0x17010000 0x0 0x1000>;

			#power-domain-cells = <1>;

		};



		aongpio: pinctrl@17020000 {

			compatible = "starfive,jh7110-aon-pinctrl";

			reg = <0x0 0x17020000 0x0 0x10000>;