Intel: perf/x86: Fix variable types for LBR registers

mainline inclusion
from mainline-v5.9-rc1
commit 3cb9d546
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I47H3V


CVE: NA

--------------------------------

commit 3cb9d546 upstream
Backport summary: backport to kernel 4.19.57 for ICX perf topdown support

The MSR variable type can be 'unsigned int', which uses less memory than
the longer 'unsigned long'. Fix 'struct x86_pmu' for that. The lbr_nr won't
be a negative number, so make it 'unsigned int' as well.

Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200613080958.132489-2-like.xu@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Jackie Liu <liuyun01@kylinos.cn>
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
Reviewed-by: Wei Li <liwei391@huawei.com>
Reviewed-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>