Commit 3e26f30f authored by Garmin.Chang's avatar Garmin.Chang Committed by Stephen Boyd
Browse files

clk: mediatek: Add MT8188 mfgcfg clock support 



Add MT8188 mfg clock controller which provides clock gate
control for GPU.

Signed-off-by: default avatarGarmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230331123621.16167-11-Garmin.Chang@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 49c9abe1

drivers/clk/mediatek/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -713,6 +713,13 @@ config COMMON_CLK_MT8188_IPESYS 
	help

	  This driver supports MediaTek MT8188 ipesys clocks.



config COMMON_CLK_MT8188_MFGCFG

	tristate "Clock driver for MediaTek MT8188 mfgcfg"

	depends on COMMON_CLK_MT8188

	default COMMON_CLK_MT8188

	help

	  This driver supports MediaTek MT8188 mfgcfg clocks.



config COMMON_CLK_MT8192

	tristate "Clock driver for MediaTek MT8192"

	depends on ARM64 || COMPILE_TEST

drivers/clk/mediatek/Makefile

+1 −0
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@@ -105,6 +105,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o 
obj-$(CONFIG_COMMON_CLK_MT8188_CAMSYS) += clk-mt8188-cam.o clk-mt8188-ccu.o

obj-$(CONFIG_COMMON_CLK_MT8188_IMGSYS) += clk-mt8188-img.o

obj-$(CONFIG_COMMON_CLK_MT8188_IPESYS) += clk-mt8188-ipe.o

obj-$(CONFIG_COMMON_CLK_MT8188_MFGCFG) += clk-mt8188-mfg.o

obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o

obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o

obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

drivers/clk/mediatek/clk-mt8188-mfg.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 MediaTek Inc.

 * Author: Garmin Chang <garmin.chang@mediatek.com>

 */



#include <dt-bindings/clock/mediatek,mt8188-clk.h>

#include <linux/clk-provider.h>

#include <linux/platform_device.h>



#include "clk-gate.h"

#include "clk-mtk.h"



static const struct mtk_gate_regs mfgcfg_cg_regs = {

	.set_ofs = 0x4,

	.clr_ofs = 0x8,

	.sta_ofs = 0x0,

};



#define GATE_MFG(_id, _name, _parent, _shift)				\

	GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs, _shift,	\

		       &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)



static const struct mtk_gate mfgcfg_clks[] = {

	GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d", "mfg_ck_fast_ref", 0),

};



static const struct mtk_clk_desc mfgcfg_desc = {

	.clks = mfgcfg_clks,

	.num_clks = ARRAY_SIZE(mfgcfg_clks),

};



static const struct of_device_id of_match_clk_mt8188_mfgcfg[] = {

	{ .compatible = "mediatek,mt8188-mfgcfg", .data = &mfgcfg_desc },

	{ /* sentinel */ }

};

MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_mfgcfg);



static struct platform_driver clk_mt8188_mfgcfg_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt8188-mfgcfg",

		.of_match_table = of_match_clk_mt8188_mfgcfg,

	},

};



module_platform_driver(clk_mt8188_mfgcfg_drv);

MODULE_LICENSE("GPL");