Commit 49c9abe1 authored by Garmin.Chang's avatar Garmin.Chang Committed by Stephen Boyd
Browse files

clk: mediatek: Add MT8188 ipesys clock support 



Add MT8188 ipesys clock controller which provides clock gate
control for Image Process Engine.

Signed-off-by: default avatarGarmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230331123621.16167-10-Garmin.Chang@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent b281039a

drivers/clk/mediatek/Kconfig

+7 −0
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@@ -706,6 +706,13 @@ config COMMON_CLK_MT8188_IMGSYS 
	help

	  This driver supports MediaTek MT8188 imgsys and imgsys2 clocks.



config COMMON_CLK_MT8188_IPESYS

	tristate "Clock driver for MediaTek MT8188 ipesys"

	depends on COMMON_CLK_MT8188_IMGSYS

	default COMMON_CLK_MT8188_IMGSYS

	help

	  This driver supports MediaTek MT8188 ipesys clocks.



config COMMON_CLK_MT8192

	tristate "Clock driver for MediaTek MT8192"

	depends on ARM64 || COMPILE_TEST

drivers/clk/mediatek/Makefile

+1 −0
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@@ -104,6 +104,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o 
				   clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o

obj-$(CONFIG_COMMON_CLK_MT8188_CAMSYS) += clk-mt8188-cam.o clk-mt8188-ccu.o

obj-$(CONFIG_COMMON_CLK_MT8188_IMGSYS) += clk-mt8188-img.o

obj-$(CONFIG_COMMON_CLK_MT8188_IPESYS) += clk-mt8188-ipe.o

obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o

obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o

obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

drivers/clk/mediatek/clk-mt8188-ipe.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 MediaTek Inc.

 * Author: Garmin Chang <garmin.chang@mediatek.com>

 */



#include <dt-bindings/clock/mediatek,mt8188-clk.h>

#include <linux/clk-provider.h>

#include <linux/platform_device.h>



#include "clk-gate.h"

#include "clk-mtk.h"



static const struct mtk_gate_regs ipe_cg_regs = {

	.set_ofs = 0x4,

	.clr_ofs = 0x8,

	.sta_ofs = 0x0,

};



#define GATE_IPE(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)



static const struct mtk_gate ipe_clks[] = {

	GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0),

	GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1),

	GATE_IPE(CLK_IPE_ME, "ipe_me", "top_ipe", 2),

	GATE_IPE(CLK_IPESYS_TOP, "ipesys_top", "top_ipe", 3),

	GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4),

};



static const struct mtk_clk_desc ipe_desc = {

	.clks = ipe_clks,

	.num_clks = ARRAY_SIZE(ipe_clks),

};



static const struct of_device_id of_match_clk_mt8188_ipe[] = {

	{ .compatible = "mediatek,mt8188-ipesys", .data = &ipe_desc },

	{ /* sentinel */ }

};

MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_ipe);



static struct platform_driver clk_mt8188_ipe_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt8188-ipe",

		.of_match_table = of_match_clk_mt8188_ipe,

	},

};



module_platform_driver(clk_mt8188_ipe_drv);

MODULE_LICENSE("GPL");