Commit 3ce5db8a authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch kvm-arm64/misc-5.15 into kvmarm-master/next 



* kvm-arm64/misc-5.15:
  : Misc improvements for 5.15:
  :
  : - Account the number of VMID-wide TLB invalidations as
  :   remote TLB flushes
  : - Fix comments in the VGIC code
  : - Cleanup the PMU IMPDEF identification
  : - Streamline the TGRAN2 usage
  : - Avoid advertising a 52bit IPA range for non-64KB configs
  : - Avoid spurious signalling when a HW-mapped interrupt is in the
  :   A+P state on entry, and in the P state on exit, but that the
  :   physical line is not pending anymore.
  : - Bunch of minor cleanups
  KVM: arm64: vgic: Resample HW pending state on deactivation
  KVM: arm64: vgic: Drop WARN from vgic_get_irq
  KVM: arm64: Drop unused REQUIRES_VIRT
  KVM: arm64: Drop check_kvm_target_cpu() based percpu probe
  KVM: arm64: Drop init_common_resources()
  KVM: arm64: Use ARM64_MIN_PARANGE_BITS as the minimum supported IPA
  arm64/mm: Add remaining ID_AA64MMFR0_PARANGE_ macros
  KVM: arm64: Restrict IPA size to maximum 48 bits on 4K and 16K page size
  arm64/mm: Define ID_AA64MMFR0_TGRAN_2_SHIFT
  KVM: arm64: perf: Replace '0xf' instances with ID_AA64DFR0_PMUVER_IMP_DEF
  KVM: arm64: Fix comments related to GICv2 PMR reporting
  KVM: arm64: Count VMID-wide TLB invalidations
  arm64/kexec: Test page size support with new TGRAN range values

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents 2d84f3ce 6e73bc90

arch/arm64/include/asm/cpufeature.h

+13 −10
Original line number Diff line number Diff line
@@ -657,7 +657,8 @@ static inline bool system_supports_4kb_granule(void) 
	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN4_SHIFT);



	return val == ID_AA64MMFR0_TGRAN4_SUPPORTED;

	return (val >= ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX);

}



static inline bool system_supports_64kb_granule(void)
@@ -669,7 +670,8 @@ static inline bool system_supports_64kb_granule(void) 
	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN64_SHIFT);



	return val == ID_AA64MMFR0_TGRAN64_SUPPORTED;

	return (val >= ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX);

}



static inline bool system_supports_16kb_granule(void)
@@ -681,7 +683,8 @@ static inline bool system_supports_16kb_granule(void) 
	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN16_SHIFT);



	return val == ID_AA64MMFR0_TGRAN16_SUPPORTED;

	return (val >= ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX);

}



static inline bool system_supports_mixed_endian_el0(void)
@@ -781,13 +784,13 @@ extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); 
static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)

{

	switch (parange) {

	case 0: return 32;

	case 1: return 36;

	case 2: return 40;

	case 3: return 42;

	case 4: return 44;

	case 5: return 48;

	case 6: return 52;

	case ID_AA64MMFR0_PARANGE_32: return 32;

	case ID_AA64MMFR0_PARANGE_36: return 36;

	case ID_AA64MMFR0_PARANGE_40: return 40;

	case ID_AA64MMFR0_PARANGE_42: return 42;

	case ID_AA64MMFR0_PARANGE_44: return 44;

	case ID_AA64MMFR0_PARANGE_48: return 48;

	case ID_AA64MMFR0_PARANGE_52: return 52;

	/*

	 * A future PE could use a value unknown to the kernel.

	 * However, by the "D10.1.4 Principles of the ID scheme

arch/arm64/include/asm/kvm_host.h

+1 −1
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 
extern unsigned int kvm_sve_max_vl;

int kvm_arm_init_sve(void);



int __attribute_const__ kvm_target_cpu(void);

u32 __attribute_const__ kvm_target_cpu(void);

int kvm_reset_vcpu(struct kvm_vcpu *vcpu);

void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);

arch/arm64/include/asm/sysreg.h

+26 −12
Original line number Diff line number Diff line
@@ -848,14 +848,25 @@ 
#define ID_AA64MMFR0_PARANGE_SHIFT	0



#define ID_AA64MMFR0_TGRAN4_NI			0xf

#define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0

#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN	0x0

#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN64_NI			0xf

#define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0

#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN	0x0

#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN16_NI			0x0

#define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1

#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN	0x1

#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX	0xf



#define ID_AA64MMFR0_PARANGE_32		0x0

#define ID_AA64MMFR0_PARANGE_36		0x1

#define ID_AA64MMFR0_PARANGE_40		0x2

#define ID_AA64MMFR0_PARANGE_42		0x3

#define ID_AA64MMFR0_PARANGE_44		0x4

#define ID_AA64MMFR0_PARANGE_48		0x5

#define ID_AA64MMFR0_PARANGE_52		0x6



#define ARM64_MIN_PARANGE_BITS		32



#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT	0x0

#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE	0x1

#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN	0x2
@@ -1028,16 +1039,19 @@ 


#if defined(CONFIG_ARM64_4K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN4_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN4_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX

#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN4_2_SHIFT

#elif defined(CONFIG_ARM64_16K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN16_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN16_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	0xF

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX

#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN16_2_SHIFT

#elif defined(CONFIG_ARM64_64K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN64_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN64_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX

#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN64_2_SHIFT

#endif



#define MVFR2_FPMISC_SHIFT		4

arch/arm64/kvm/arm.c

+2 −25
Original line number Diff line number Diff line
@@ -42,10 +42,6 @@ 
#include <kvm/arm_pmu.h>

#include <kvm/arm_psci.h>



#ifdef REQUIRES_VIRT

__asm__(".arch_extension	virt");

#endif



static enum kvm_mode kvm_mode = KVM_MODE_DEFAULT;

DEFINE_STATIC_KEY_FALSE(kvm_protected_mode_initialized);
@@ -1035,7 +1031,7 @@ static int kvm_vcpu_set_target(struct kvm_vcpu *vcpu, 
			       const struct kvm_vcpu_init *init)

{

	unsigned int i, ret;

	int phys_target = kvm_target_cpu();

	u32 phys_target = kvm_target_cpu();



	if (init->target != phys_target)

		return -EINVAL;
@@ -1696,11 +1692,6 @@ static bool init_psci_relay(void) 
	return true;

}



static int init_common_resources(void)

{

	return kvm_set_ipa_limit();

}



static int init_subsystems(void)

{

	int err = 0;
@@ -2015,11 +2006,6 @@ static int finalize_hyp_mode(void) 
	return 0;

}



static void check_kvm_target_cpu(void *ret)

{

	*(int *)ret = kvm_target_cpu();

}



struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr)

{

	struct kvm_vcpu *vcpu;
@@ -2079,7 +2065,6 @@ void kvm_arch_irq_bypass_start(struct irq_bypass_consumer *cons) 
int kvm_arch_init(void *opaque)

{

	int err;

	int ret, cpu;

	bool in_hyp_mode;



	if (!is_hyp_mode_available()) {
@@ -2094,15 +2079,7 @@ int kvm_arch_init(void *opaque) 
		kvm_info("Guests without required CPU erratum workarounds can deadlock system!\n" \

			 "Only trusted guests should be used on this system.\n");



	for_each_online_cpu(cpu) {

		smp_call_function_single(cpu, check_kvm_target_cpu, &ret, 1);

		if (ret < 0) {

			kvm_err("Error, CPU %d not supported!\n", cpu);

			return -ENODEV;

		}

	}



	err = init_common_resources();

	err = kvm_set_ipa_limit();

	if (err)

		return err;

arch/arm64/kvm/guest.c

+2 −2
Original line number Diff line number Diff line
@@ -842,7 +842,7 @@ int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 
	return 0;

}



int __attribute_const__ kvm_target_cpu(void)

u32 __attribute_const__ kvm_target_cpu(void)

{

	unsigned long implementor = read_cpuid_implementor();

	unsigned long part_number = read_cpuid_part_number();
@@ -874,7 +874,7 @@ int __attribute_const__ kvm_target_cpu(void) 


int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init)

{

	int target = kvm_target_cpu();

	u32 target = kvm_target_cpu();



	if (target < 0)

		return -ENODEV;