Unverified Commit 3ca507bf authored by Chancel Liu's avatar Chancel Liu Committed by Mark Brown
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ASoC: wm8962: Wait for updated value of WM8962_CLOCKING1 register 



DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
correct frequency of LRCLK and BCLK. Sometimes the read-only value
can't be updated timely after enabling SYSCLK. This results in wrong
calculation values. Delay is introduced here to wait for newest value
from register. The time of the delay should be at least 500~1000us
according to test.

Signed-off-by: default avatarChancel Liu <chancel.liu@nxp.com>
Acked-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20221109121354.123958-1-chancel.liu@nxp.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 7d945b04

sound/soc/codecs/wm8962.c

+8 −0
Original line number Diff line number Diff line
@@ -2503,6 +2503,14 @@ static void wm8962_configure_bclk(struct snd_soc_component *component) 
		snd_soc_component_update_bits(component, WM8962_CLOCKING2,

				WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);



	/* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate

	 * correct frequency of LRCLK and BCLK. Sometimes the read-only value

	 * can't be updated timely after enabling SYSCLK. This results in wrong

	 * calculation values. Delay is introduced here to wait for newest

	 * value from register. The time of the delay should be at least

	 * 500~1000us according to test.

	 */

	usleep_range(500, 1000);

	dspclk = snd_soc_component_read(component, WM8962_CLOCKING1);



	if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)