Commit 3ba2d41d authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-ralink' into clk-next 

 - Proper clk driver for Mediatek MT7621 SoCs

* clk-ralink:
  MAINTAINERS: add MT7621 CLOCK maintainer
  staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'
  staging: mt7621-dts: make use of new 'mt7621-clk'
  clk: ralink: add clock driver for mt7621 SoC
  dt: bindings: add mt7621-sysc device tree binding documentation
  dt-bindings: clock: add dt binding header for mt7621 clocks
parents bbc3b403 0ec3815a

Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MT7621 Clock Device Tree Bindings



maintainers:

  - Sergio Paracuellos <sergio.paracuellos@gmail.com>



description: |

  The MT7621 has a PLL controller from where the cpu clock is provided

  as well as derived clocks for the bus and the peripherals. It also

  can gate SoC device clocks.



  Each clock is assigned an identifier and client nodes use this identifier

  to specify the clock which they consume.



  All these identifiers could be found in:

  [1]: <include/dt-bindings/clock/mt7621-clk.h>.



  The clocks are provided inside a system controller node.



properties:

  compatible:

    items:

      - const: mediatek,mt7621-sysc

      - const: syscon



  reg:

    maxItems: 1



  "#clock-cells":

    description:

      The first cell indicates the clock number, see [1] for available

      clocks.

    const: 1



  ralink,memctl:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      phandle of syscon used to control memory registers



  clock-output-names:

    maxItems: 8



required:

  - compatible

  - reg

  - '#clock-cells'

  - ralink,memctl



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/mt7621-clk.h>



    sysc: sysc@0 {

      compatible = "mediatek,mt7621-sysc", "syscon";

      reg = <0x0 0x100>;

      #clock-cells = <1>;

      ralink,memctl = <&memc>;

      clock-output-names = "xtal", "cpu", "bus",

                           "50m", "125m", "150m",

                           "250m", "270m";

    };

MAINTAINERS

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@@ -11295,6 +11295,12 @@ L: linux-wireless@vger.kernel.org 
S:	Maintained

F:	drivers/net/wireless/mediatek/mt7601u/









MEDIATEK MT7621 CLOCK DRIVER









M:	Sergio Paracuellos <sergio.paracuellos@gmail.com>









S:	Maintained









F:	Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml









F:	drivers/clk/ralink/clk-mt7621.c

















MEDIATEK MT7621/28/88 I2C DRIVER









M:	Stefan Roese <sr@denx.de>









L:	linux-i2c@vger.kernel.org
































arch/mips/ralink/mt7621.c



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−3






























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@@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void)

















void __init ralink_of_remap(void)









{









	rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");









	rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");









	rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");









	rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");



















	if (!rt_sysc_membase || !rt_memc_membase)









		panic("Failed to remap core resources");








@@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)

















	if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {









		name = "MT7621";









		soc_info->compatible = "mtk,mt7621-soc";









		soc_info->compatible = "mediatek,mt7621-soc";









	} else {









		panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);









	}
































drivers/clk/Kconfig



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@@ -390,6 +390,7 @@ source "drivers/clk/meson/Kconfig"







source "drivers/clk/mstar/Kconfig"









source "drivers/clk/mvebu/Kconfig"









source "drivers/clk/qcom/Kconfig"









source "drivers/clk/ralink/Kconfig"









source "drivers/clk/renesas/Kconfig"









source "drivers/clk/rockchip/Kconfig"









source "drivers/clk/samsung/Kconfig"
































drivers/clk/Makefile



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@@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)		+= nxp/







obj-$(CONFIG_MACH_PISTACHIO)		+= pistachio/









obj-$(CONFIG_COMMON_CLK_PXA)		+= pxa/









obj-$(CONFIG_COMMON_CLK_QCOM)		+= qcom/









obj-y					+= ralink/









obj-y					+= renesas/









obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/









obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/