Commit 39bc5006 authored by Rob Herring's avatar Rob Herring Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: Centralize link gen setting 

keystone would force gen2 if no DT property. Now it relies on the
PCI_EXP_LNKCAP value.

Link: https://lore.kernel.org/r/20200821035420.380495-35-robh@kernel.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
parent b04a6b9d

drivers/pci/controller/dwc/pci-dra7xx.c

+0 −26
Original line number Diff line number Diff line
@@ -89,7 +89,6 @@ struct dra7xx_pcie { 
	void __iomem		*base;		/* DT ti_conf */

	int			phy_count;	/* DT phy-names count */

	struct phy		**phy;

	int			link_gen;

	struct irq_domain	*irq_domain;

	enum dw_pcie_device_mode mode;

};
@@ -140,33 +139,12 @@ static int dra7xx_pcie_establish_link(struct dw_pcie *pci) 
	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);

	struct device *dev = pci->dev;

	u32 reg;

	u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);



	if (dw_pcie_link_up(pci)) {

		dev_err(dev, "link is already up\n");

		return 0;

	}



	if (dra7xx->link_gen == 1) {

		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,

			     4, &reg);

		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {

			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);

			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;

			dw_pcie_write(pci->dbi_base + exp_cap_off +

				      PCI_EXP_LNKCAP, 4, reg);

		}



		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,

			     2, &reg);

		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {

			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);

			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;

			dw_pcie_write(pci->dbi_base + exp_cap_off +

				      PCI_EXP_LNKCTL2, 2, reg);

		}

	}



	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);

	reg |= LTSSM_EN;

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
@@ -935,10 +913,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) 
	reg &= ~LTSSM_EN;

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);



	dra7xx->link_gen = of_pci_get_max_link_speed(np);

	if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)

		dra7xx->link_gen = 2;



	switch (mode) {

	case DW_PCIE_RC_TYPE:

		if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {

drivers/pci/controller/dwc/pci-imx6.c

+3 −6
Original line number Diff line number Diff line
@@ -79,7 +79,6 @@ struct imx6_pcie { 
	u32			tx_deemph_gen2_6db;

	u32			tx_swing_full;

	u32			tx_swing_low;

	int			link_gen;

	struct regulator	*vpcie;

	void __iomem		*phy_base;
@@ -771,7 +770,7 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) 
	if (ret)

		goto err_reset_phy;



	if (imx6_pcie->link_gen == 2) {

	if (pci->link_gen == 2) {

		/* Allow Gen2 mode after the link is up. */

		tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);

		tmp &= ~PCI_EXP_LNKCAP_SLS;
@@ -1153,10 +1152,8 @@ static int imx6_pcie_probe(struct platform_device *pdev) 
		imx6_pcie->tx_swing_low = 127;



	/* Limit link speed */

	ret = of_property_read_u32(node, "fsl,max-link-speed",

				   &imx6_pcie->link_gen);

	if (ret)

		imx6_pcie->link_gen = 1;

	pci->link_gen = 1;

	ret = of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);



	imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");

	if (IS_ERR(imx6_pcie->vpcie)) {

drivers/pci/controller/dwc/pci-keystone.c

+0 −33
Original line number Diff line number Diff line
@@ -1107,32 +1107,6 @@ static int ks_pcie_am654_set_mode(struct device *dev, 
	return 0;

}



static void ks_pcie_set_link_speed(struct dw_pcie *pci, int link_speed)

{

	u32 val;

	u32 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);



	dw_pcie_dbi_ro_wr_en(pci);



	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);

	if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) {

		val &= ~((u32)PCI_EXP_LNKCAP_SLS);

		val |= link_speed;

		dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP,

				   val);

	}



	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);

	if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) {

		val &= ~((u32)PCI_EXP_LNKCAP_SLS);

		val |= link_speed;

		dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2,

				   val);

	}



	dw_pcie_dbi_ro_wr_dis(pci);

}



static const struct ks_pcie_of_data ks_pcie_rc_of_data = {

	.host_ops = &ks_pcie_host_ops,

	.version = 0x365A,
@@ -1185,7 +1159,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) 
	unsigned int version;

	void __iomem *base;

	struct phy **phy;

	int link_speed;

	u32 num_lanes;

	char name[10];

	int ret;
@@ -1320,12 +1293,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) 
			goto err_get_sync;

	}



	link_speed = of_pci_get_max_link_speed(np);

	if (link_speed < 0)

		link_speed = 2;



	ks_pcie_set_link_speed(pci, link_speed);



	switch (mode) {

	case DW_PCIE_RC_TYPE:

		if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) {

drivers/pci/controller/dwc/pcie-designware-ep.c

+9 −2
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ 
#include <linux/pci-epc.h>

#include <linux/pci-epf.h>



#include "../../pci.h"



void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)

{

	struct pci_epc *epc = ep->epc;
@@ -519,18 +521,20 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) 
	ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);



	offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);



	dw_pcie_dbi_ro_wr_en(pci);



	if (offset) {

		reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);

		nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>

			PCI_REBAR_CTRL_NBAR_SHIFT;



		dw_pcie_dbi_ro_wr_en(pci);

		for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)

			dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);

		dw_pcie_dbi_ro_wr_dis(pci);

	}



	dw_pcie_setup(pci);

	dw_pcie_dbi_ro_wr_dis(pci);



	return 0;

}
@@ -591,6 +595,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) 
		return -ENOMEM;

	ep->outbound_addr = addr;



	if (pci->link_gen < 1)

		pci->link_gen = of_pci_get_max_link_speed(np);



	epc = devm_pci_epc_create(dev, &epc_ops);

	if (IS_ERR(epc)) {

		dev_err(dev, "Failed to create epc device\n");

drivers/pci/controller/dwc/pcie-designware-host.c

+3 −0
Original line number Diff line number Diff line
@@ -361,6 +361,9 @@ int dw_pcie_host_init(struct pcie_port *pp) 
	if (ret)

		pci->num_viewport = 2;



	if (pci->link_gen < 1)

		pci->link_gen = of_pci_get_max_link_speed(np);



	if (pci_msi_enabled()) {

		/*

		 * If a specific SoC driver needs to change the