Commit b04a6b9d authored by Rob Herring's avatar Rob Herring Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: Make ATU accessors private 

The ATU registers are only accessed in pcie-designware.c and can be private
to it.

Link: https://lore.kernel.org/r/20200821035420.380495-34-robh@kernel.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
parent 903d69f8

drivers/pci/controller/dwc/pcie-designware.c

+6 −6
Original line number Diff line number Diff line
@@ -180,31 +180,31 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 
		dev_err(pci->dev, "write DBI address failed\n");

}



u32 dw_pcie_read_atu(struct dw_pcie *pci, u32 reg, size_t size)

static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg)

{

	int ret;

	u32 val;



	if (pci->ops->read_dbi)

		return pci->ops->read_dbi(pci, pci->atu_base, reg, size);

		return pci->ops->read_dbi(pci, pci->atu_base, reg, 4);



	ret = dw_pcie_read(pci->atu_base + reg, size, &val);

	ret = dw_pcie_read(pci->atu_base + reg, 4, &val);

	if (ret)

		dev_err(pci->dev, "Read ATU address failed\n");



	return val;

}



void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 val)

static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)

{

	int ret;



	if (pci->ops->write_dbi) {

		pci->ops->write_dbi(pci, pci->atu_base, reg, size, val);

		pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val);

		return;

	}



	ret = dw_pcie_write(pci->atu_base + reg, size, val);

	ret = dw_pcie_write(pci->atu_base + reg, 4, val);

	if (ret)

		dev_err(pci->dev, "Write ATU address failed\n");

}

drivers/pci/controller/dwc/pcie-designware.h

+0 −12
Original line number Diff line number Diff line
@@ -268,8 +268,6 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val); 
u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size);

void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val);

void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);

u32 dw_pcie_read_atu(struct dw_pcie *pci, u32 reg, size_t size);

void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 val);

int dw_pcie_link_up(struct dw_pcie *pci);

void dw_pcie_upconfig_setup(struct dw_pcie *pci);

void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen);
@@ -319,16 +317,6 @@ static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) 
	dw_pcie_write_dbi2(pci, reg, 0x4, val);

}



static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)

{

	dw_pcie_write_atu(pci, reg, 0x4, val);

}



static inline u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg)

{

	return dw_pcie_read_atu(pci, reg, 0x4);

}



static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)

{

	u32 reg;