Commit 387b5a8d authored by Nick Forrington's avatar Nick Forrington Committed by Arnaldo Carvalho de Melo
Browse files

perf vendors events arm64: Arm Cortex-A75 

Add PMU events for Arm Cortex-A75
Add corresponding common events
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a75.json

which is based on PMU event descriptions from the Arm Cortex-A75 Technical
Reference Manual.

Common event data based on:
https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json

which is based on PMU event descriptions found in the Arm Architecture
Reference Manual:
https://developer.arm.com/documentation/ddi0487/

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json



which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Signed-off-by: default avatarNick Forrington <nick.forrington@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Andrew Kilroy <andrew.kilroy@arm.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20220520181455.340344-8-nick.forrington@arm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 64a091c6

tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json

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[

    {

        "ArchStdEvent": "BR_MIS_PRED"

    },

    {

        "ArchStdEvent": "BR_PRED"

    },

    {

        "ArchStdEvent": "BR_INDIRECT_SPEC"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json

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[

    {

        "ArchStdEvent": "CPU_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS"

    },

    {

        "ArchStdEvent": "BUS_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_WR"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json

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[

    {

        "ArchStdEvent": "L1I_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1I_CACHE"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L2D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L1D_CACHE_ALLOCATE"

    },

    {

        "ArchStdEvent": "L2D_CACHE_ALLOCATE"

    },

    {

        "ArchStdEvent": "L1D_TLB"

    },

    {

        "ArchStdEvent": "L1I_TLB"

    },

    {

        "ArchStdEvent": "L3D_CACHE_ALLOCATE"

    },

    {

        "ArchStdEvent": "L3D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L3D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L2D_TLB"

    },

    {

        "ArchStdEvent": "L2I_TLB"

    },

    {

        "ArchStdEvent": "DTLB_WALK"

    },

    {

        "ArchStdEvent": "ITLB_WALK"

    },

    {

        "ArchStdEvent": "LL_CACHE_RD"

    },

    {

        "ArchStdEvent": "LL_CACHE_MISS_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L1D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L2D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L2D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L3D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L3D_CACHE_REFILL_RD"

    },

    {

        "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",

        "EventCode": "0xC2",

        "EventName": "I_TAG_RAM_RD",

        "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"

    },

    {

        "PublicDescription": "Number of ways read in the instruction cache - Data RAM",

        "EventCode": "0xC3",

        "EventName": "I_DATA_RAM_RD",

        "BriefDescription": "Number of ways read in the instruction cache - Data RAM"

    },

    {

        "PublicDescription": "Number of ways read in the instruction BTAC RAM",

        "EventCode": "0xC4",

        "EventName": "I_BTAC_RAM_RD",

        "BriefDescription": "Number of ways read in the instruction BTAC RAM"

    },

    {

        "PublicDescription": "Level 1 PLD TLB refill",

        "EventCode": "0xE7",

        "EventName": "L1PLD_TLB_REFILL",

        "BriefDescription": "Level 1 PLD TLB refill"

    },

    {

        "PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts software and hardware prefetches at Level 2",

        "EventCode": "0xE8",

        "EventName": "L2PLD_TLB",

        "BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts software and hardware prefetches at Level 2"

    },

    {

        "PublicDescription": "Level 1 TLB flush",

        "EventCode": "0xE9",

        "EventName": "UTLB_FLUSH",

        "BriefDescription": "Level 1 TLB flush"

    },

    {

        "PublicDescription": "Level 2 TLB access",

        "EventCode": "0xEA",

        "EventName": "TLB_ACCESS",

        "BriefDescription": "Level 2 TLB access"

    },

    {

        "PublicDescription": "Level 1 preload TLB access. This event only counts software and hardware prefetches at Level 1. This event counts all accesses to the preload data micro TLB, that is L1 prefetcher and preload instructions. This event does not take into account whether the MMU is enabled or not",

        "EventCode": "0xEB",

        "EventName": "L1PLD_TLB",

        "BriefDescription": "Level 1 preload TLB access. This event only counts software and hardware prefetches at Level 1. This event counts all accesses to the preload data micro TLB, that is L1 prefetcher and preload instructions. This event does not take into account whether the MMU is enabled or not"

    },

    {

        "PublicDescription": "Prefetch access to unified TLB that caused a page table walk. This event counts software and hardware prefetches",

        "EventCode": "0xEC",

        "EventName": "PLDTLB_WALK",

        "BriefDescription": "Prefetch access to unified TLB that caused a page table walk. This event counts software and hardware prefetches"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json

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[

    {

        "PublicDescription": "ETM trace unit output 0",

        "EventCode": "0xDE",

        "EventName": "ETM_EXT_OUT0",

        "BriefDescription": "ETM trace unit output 0"

    },

    {

        "PublicDescription": "ETM trace unit output 1",

        "EventCode": "0xDF",

        "EventName": "ETM_EXT_OUT1",

        "BriefDescription": "ETM trace unit output 1"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a75/exception.json

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[

    {

        "ArchStdEvent": "EXC_TAKEN"

    },

    {

        "ArchStdEvent": "EXC_UNDEF"

    },

    {

        "ArchStdEvent": "EXC_HVC"

    },

    {

        "PublicDescription": "Number of traps to hypervisor. This event counts the number of exception traps taken to EL2, excluding HVC instructions. This event is set every time that an exception is executed because of a decoded trap to the hypervisor. CCFAIL exceptions and traps caused by HVC instructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1",

        "EventCode": "0xDC",

        "EventName": "EXC_TRAP_HYP",

        "BriefDescription": "Number of traps to hypervisor. This event counts the number of exception traps taken to EL2, excluding HVC instructions. This event is set every time that an exception is executed because of a decoded trap to the hypervisor. CCFAIL exceptions and traps caused by HVC instructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1"

    }

]