Commit 64a091c6 authored by Nick Forrington's avatar Nick Forrington Committed by Arnaldo Carvalho de Melo
Browse files

perf vendors events arm64: Arm Cortex-A73 

Add PMU events for Arm Cortex-A73
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a73.json

which is based on PMU event descriptions from the Arm Cortex-A73 Technical
Reference Manual.

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json



which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Signed-off-by: default avatarNick Forrington <nick.forrington@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Andrew Kilroy <andrew.kilroy@arm.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20220520181455.340344-7-nick.forrington@arm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 6951dee8

tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json

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+11 −0
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[

    {

        "ArchStdEvent": "BR_MIS_PRED"

    },

    {

        "ArchStdEvent": "BR_PRED"

    },

    {

        "ArchStdEvent": "BR_INDIRECT_SPEC"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json

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[

    {

        "ArchStdEvent": "CPU_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS"

    },

    {

        "ArchStdEvent": "BUS_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_SHARED"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_NOT_SHARED"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_NORMAL"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_PERIPH"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json

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Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "L1I_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1I_CACHE"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L2D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L1D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L2D_CACHE_INVAL"

    },

    {

        "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",

        "EventCode": "0xC2",

        "EventName": "I_TAG_RAM_RD",

        "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"

    },

    {

        "PublicDescription": "Number of ways read in the instruction cache - Data RAM",

        "EventCode": "0xC3",

        "EventName": "I_DATA_RAM_RD",

        "BriefDescription": "Number of ways read in the instruction cache - Data RAM"

    },

    {

        "PublicDescription": "Number of ways read in the instruction BTAC RAM",

        "EventCode": "0xC4",

        "EventName": "I_BTAC_RAM_RD",

        "BriefDescription": "Number of ways read in the instruction BTAC RAM"

    },

    {

        "PublicDescription": "Level 1 PLD TLB refill",

        "EventCode": "0xE7",

        "EventName": "PLD_UTLB_REFILL",

        "BriefDescription": "Level 1 PLD TLB refill"

    },

    {

        "PublicDescription": "Level 1 CP15 TLB refill",

        "EventCode": "0xE8",

        "EventName": "CP15_UTLB_REFILL",

        "BriefDescription": "Level 1 CP15 TLB refill"

    },

    {

        "PublicDescription": "Level 1 TLB flush",

        "EventCode": "0xE9",

        "EventName": "UTLB_FLUSH",

        "BriefDescription": "Level 1 TLB flush"

    },

    {

        "PublicDescription": "Level 2 TLB access",

        "EventCode": "0xEA",

        "EventName": "TLB_ACCESS",

        "BriefDescription": "Level 2 TLB access"

    },

    {

        "PublicDescription": "Level 2 TLB miss",

        "EventCode": "0xEB",

        "EventName": "TLB_MISS",

        "BriefDescription": "Level 2 TLB miss"

    },

    {

        "PublicDescription": "Data cache hit in itself due to VIPT aliasing",

        "EventCode": "0xEC",

        "EventName": "DCACHE_SELF_HIT_VIPT",

        "BriefDescription": "Data cache hit in itself due to VIPT aliasing"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json

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[

    {

        "PublicDescription": "ETM trace unit output 0",

        "EventCode": "0xDE",

        "EventName": "ETM_EXT_OUT0",

        "BriefDescription": "ETM trace unit output 0"

    },

    {

        "PublicDescription": "ETM trace unit output 1",

        "EventCode": "0xDF",

        "EventName": "ETM_EXT_OUT1",

        "BriefDescription": "ETM trace unit output 1"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a73/exception.json

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[

    {

        "ArchStdEvent": "EXC_TAKEN"

    },

    {

        "ArchStdEvent": "EXC_HVC"

    },

    {

        "PublicDescription": "Number of Traps to hypervisor",

        "EventCode": "0xDC",

        "EventName": "EXC_TRAP_HYP",

        "BriefDescription": "Number of Traps to hypervisor"

    }

]