Commit 381a3083 authored by Terry Bowman's avatar Terry Bowman Committed by Wolfram Sang
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i2c: piix4: Add EFCH MMIO support for SMBus port select 



AMD processors include registers capable of selecting between 2 SMBus
ports. Port selection is made during each user access by writing to
FCH::PM::DECODEEN[smbus0sel]. Change the driver to use MMIO during
SMBus port selection because cd6h/cd7h port I/O is not available on
later AMD processors.

Signed-off-by: default avatarTerry Bowman <terry.bowman@amd.com>
Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: default avatarJean Delvare <jdelvare@suse.de>
Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
parent 46967bc1

drivers/i2c/busses/i2c-piix4.c

+12 −3
Original line number Diff line number Diff line
@@ -753,10 +753,19 @@ static void piix4_imc_wakeup(void) 
	release_region(KERNCZ_IMC_IDX, 2);

}



static int piix4_sb800_port_sel(u8 port)

static int piix4_sb800_port_sel(u8 port, struct sb800_mmio_cfg *mmio_cfg)

{

	u8 smba_en_lo, val;



	if (mmio_cfg->use_mmio) {

		smba_en_lo = ioread8(mmio_cfg->addr + piix4_port_sel_sb800);

		val = (smba_en_lo & ~piix4_port_mask_sb800) | port;

		if (smba_en_lo != val)

			iowrite8(val, mmio_cfg->addr + piix4_port_sel_sb800);



		return (smba_en_lo & piix4_port_mask_sb800);

	}



	outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);

	smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
@@ -843,12 +852,12 @@ static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, 
		}

	}



	prev_port = piix4_sb800_port_sel(adapdata->port);

	prev_port = piix4_sb800_port_sel(adapdata->port, &adapdata->mmio_cfg);



	retval = piix4_access(adap, addr, flags, read_write,

			      command, size, data);



	piix4_sb800_port_sel(prev_port);

	piix4_sb800_port_sel(prev_port, &adapdata->mmio_cfg);



	/* Release the semaphore */

	outb_p(smbslvcnt | 0x20, SMBSLVCNT);