Commit 36fcf381 authored Sep 22, 2023 by Linus Torvalds

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:
 "Small crop of relatively boring arm64 fixes for -rc3.

  That's not to say we don't have any juicy bugs, however, it's just
  that fixes for those are likely to come via -mm and -tip for a hugetlb
  and an atomics issue respectively. I get left with the
  documentation...

   - Fix detection of "ClearBHB" and "Hinted Conditional Branch" features

   - Fix broken wildcarding for Arm PMU MAINTAINERS entry

   - Add missing documentation for userspace-visible ID register fields"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: Document missing userspace visible fields in ID_AA64ISAR2_EL1
  arm64/hbc: Document HWCAP2_HBC
  arm64/sme: Include ID_AA64PFR1_EL1.SME in cpu-feature-registers.rst
  arm64: cpufeature: Fix CLRBHB and BC detection
  MAINTAINERS: Use wildcard pattern for ARM PMU headers

parents b61ec8d0 44a5b6b5

Documentation/arch/arm64/cpu-feature-registers.rst

+12 −0

Original line number	Diff line number	Diff line
		@@ -175,6 +175,8 @@ infrastructure:
		+------------------------------+---------+---------+
		\| Name \| bits \| visible \|
		+------------------------------+---------+---------+
		\| SME \| [27-24] \| y \|
		+------------------------------+---------+---------+
		\| MTE \| [11-8] \| y \|
		+------------------------------+---------+---------+
		\| SSBS \| [7-4] \| y \|
		@@ -288,8 +290,18 @@ infrastructure:
		+------------------------------+---------+---------+
		\| Name \| bits \| visible \|
		+------------------------------+---------+---------+
		\| CSSC \| [55-52] \| y \|
		+------------------------------+---------+---------+
		\| RPRFM \| [51-48] \| y \|
		+------------------------------+---------+---------+
		\| BC \| [23-20] \| y \|
		+------------------------------+---------+---------+
		\| MOPS \| [19-16] \| y \|
		+------------------------------+---------+---------+
		\| APA3 \| [15-12] \| y \|
		+------------------------------+---------+---------+
		\| GPA3 \| [11-8] \| y \|
		+------------------------------+---------+---------+
		\| RPRES \| [7-4] \| y \|
		+------------------------------+---------+---------+
		\| WFXT \| [3-0] \| y \|

Documentation/arch/arm64/elf_hwcaps.rst

+3 −0

Original line number	Diff line number	Diff line
		@@ -305,6 +305,9 @@ HWCAP2_SMEF16F16
		HWCAP2_MOPS
		Functionality implied by ID_AA64ISAR2_EL1.MOPS == 0b0001.

		HWCAP2_HBC
		Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.

		4. Unused AT_HWCAP bits
		-----------------------

MAINTAINERS

+1 −1

Original line number	Diff line number	Diff line
		@@ -1662,7 +1662,7 @@ F: arch/arm*/include/asm/perf_event.h
		F: arch/arm*/kernel/hw_breakpoint.c
		F: arch/arm/kernel/perf_
		F: drivers/perf/
		F: include/linux/perf/arm_pmu.h
		F: include/linux/perf/arm_pmu*.h

		ARM PORT
		M: Russell King <linux@armlinux.org.uk>

arch/arm64/include/asm/cpufeature.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -663,7 +663,7 @@ static inline bool supports_clearbhb(int scope)
		isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);

		return cpuid_feature_extract_unsigned_field(isar2,
		ID_AA64ISAR2_EL1_BC_SHIFT);
		ID_AA64ISAR2_EL1_CLRBHB_SHIFT);
		}

		const struct cpumask *system_32bit_el0_cpumask(void);

arch/arm64/kernel/cpufeature.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -222,7 +222,8 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
		static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
		ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
		FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),