Commit 36c5dde5 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
Browse files

drm/msm/dsi: stop passing src_pll_id to the phy_enable call 



Phy driver already knows the source PLL id basing on the set usecase and
the current PLL id. Stop passing it to the phy_enable call. As a
reminder, dsi manager will always use DSI 0 as a clock master in a slave
mode, so PLL 0 is always a clocksource for DSI 0 and it is always a
clocksource for DSI 1 too unless DSI 1 is used in the standalone mode.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Reviewed-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Link: https://lore.kernel.org/r/20210331105735.3690009-25-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 6e2ad9c3

drivers/gpu/drm/msm/dsi/dsi.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -162,7 +162,7 @@ struct msm_dsi_phy_clk_request { 




void msm_dsi_phy_driver_register(void);

void msm_dsi_phy_driver_register(void);

void msm_dsi_phy_driver_unregister(void);

void msm_dsi_phy_driver_unregister(void);

int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,

int msm_dsi_phy_enable(struct msm_dsi_phy *phy,

			struct msm_dsi_phy_clk_request *clk_req);

			struct msm_dsi_phy_clk_request *clk_req);

void msm_dsi_phy_disable(struct msm_dsi_phy *phy);

void msm_dsi_phy_disable(struct msm_dsi_phy *phy);

void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,

void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,

drivers/gpu/drm/msm/dsi/dsi_manager.c

+5 −6
Original line number Original line Diff line number Diff line
@@ -114,7 +114,7 @@ static int dsi_mgr_setup_components(int id) 
	return ret;

	return ret;

}

}





static int enable_phy(struct msm_dsi *msm_dsi, int src_pll_id,

static int enable_phy(struct msm_dsi *msm_dsi,

		      struct msm_dsi_phy_shared_timings *shared_timings)

		      struct msm_dsi_phy_shared_timings *shared_timings)

{

{

	struct msm_dsi_phy_clk_request clk_req;

	struct msm_dsi_phy_clk_request clk_req;
@@ -123,7 +123,7 @@ static int enable_phy(struct msm_dsi *msm_dsi, int src_pll_id, 




	msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_dual_dsi);

	msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_dual_dsi);





	ret = msm_dsi_phy_enable(msm_dsi->phy, src_pll_id, &clk_req);

	ret = msm_dsi_phy_enable(msm_dsi->phy, &clk_req);

	msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings);

	msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings);





	return ret;

	return ret;
@@ -136,7 +136,6 @@ dsi_mgr_phy_enable(int id, 
	struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);

	struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);

	struct msm_dsi *mdsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);

	struct msm_dsi *mdsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);

	struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);

	struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);

	int src_pll_id = IS_DUAL_DSI() ? DSI_CLOCK_MASTER : id;

	int ret;

	int ret;





	/* In case of dual DSI, some registers in PHY1 have been programmed

	/* In case of dual DSI, some registers in PHY1 have been programmed
@@ -149,11 +148,11 @@ dsi_mgr_phy_enable(int id, 
			msm_dsi_host_reset_phy(mdsi->host);

			msm_dsi_host_reset_phy(mdsi->host);

			msm_dsi_host_reset_phy(sdsi->host);

			msm_dsi_host_reset_phy(sdsi->host);





			ret = enable_phy(mdsi, src_pll_id,

			ret = enable_phy(mdsi,

					 &shared_timings[DSI_CLOCK_MASTER]);

					 &shared_timings[DSI_CLOCK_MASTER]);

			if (ret)

			if (ret)

				return ret;

				return ret;

			ret = enable_phy(sdsi, src_pll_id,

			ret = enable_phy(sdsi,

					 &shared_timings[DSI_CLOCK_SLAVE]);

					 &shared_timings[DSI_CLOCK_SLAVE]);

			if (ret) {

			if (ret) {

				msm_dsi_phy_disable(mdsi->phy);

				msm_dsi_phy_disable(mdsi->phy);
@@ -162,7 +161,7 @@ dsi_mgr_phy_enable(int id, 
		}

		}

	} else {

	} else {

		msm_dsi_host_reset_phy(msm_dsi->host);

		msm_dsi_host_reset_phy(msm_dsi->host);

		ret = enable_phy(msm_dsi, src_pll_id, &shared_timings[id]);

		ret = enable_phy(msm_dsi, &shared_timings[id]);

		if (ret)

		if (ret)

			return ret;

			return ret;

	}

	}

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -753,7 +753,7 @@ void __exit msm_dsi_phy_driver_unregister(void) 
	platform_driver_unregister(&dsi_phy_platform_driver);

	platform_driver_unregister(&dsi_phy_platform_driver);

}

}





int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,

int msm_dsi_phy_enable(struct msm_dsi_phy *phy,

			struct msm_dsi_phy_clk_request *clk_req)

			struct msm_dsi_phy_clk_request *clk_req)

{

{

	struct device *dev = &phy->pdev->dev;

	struct device *dev = &phy->pdev->dev;
@@ -776,7 +776,7 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, 
		goto reg_en_fail;

		goto reg_en_fail;

	}

	}





	ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);

	ret = phy->cfg->ops.enable(phy, clk_req);

	if (ret) {

	if (ret) {

		DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);

		DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);

		goto phy_en_fail;

		goto phy_en_fail;

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -19,7 +19,7 @@ 




struct msm_dsi_phy_ops {

struct msm_dsi_phy_ops {

	int (*pll_init)(struct msm_dsi_phy *phy);

	int (*pll_init)(struct msm_dsi_phy *phy);

	int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,

	int (*enable)(struct msm_dsi_phy *phy,

			struct msm_dsi_phy_clk_request *clk_req);

			struct msm_dsi_phy_clk_request *clk_req);

	void (*disable)(struct msm_dsi_phy *phy);

	void (*disable)(struct msm_dsi_phy *phy);

	void (*save_pll_state)(struct msm_dsi_phy *phy);

	void (*save_pll_state)(struct msm_dsi_phy *phy);

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -788,7 +788,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy) 
	}

	}

}

}





static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,

static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy,

			       struct msm_dsi_phy_clk_request *clk_req)

			       struct msm_dsi_phy_clk_request *clk_req)

{

{

	int ret;

	int ret;