Commit 6e2ad9c3 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
Browse files

drm/msm/dsi: inline msm_dsi_phy_set_src_pll 



The src_truthtable config is not used for some of phys, which use other
means of configuring the master/slave usecases. Inline this function
with the goal of removing src_pll_id argument in the next commit.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Reviewed-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Link: https://lore.kernel.org/r/20210331105735.3690009-24-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 001d8dc3

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+0 −17
Original line number Original line Diff line number Diff line
@@ -461,23 +461,6 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, 
	return 0;

	return 0;

}

}





void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,

				u32 bit_mask)

{

	int phy_id = phy->id;

	u32 val;



	if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))

		return;



	val = dsi_phy_read(phy->base + reg);



	if (phy->cfg->src_pll_truthtable[phy_id][pll_id])

		dsi_phy_write(phy->base + reg, val | bit_mask);

	else

		dsi_phy_write(phy->base + reg, val & (~bit_mask));

}



static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)

static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)

{

{

	struct regulator_bulk_data *s = phy->supplies;

	struct regulator_bulk_data *s = phy->supplies;

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+0 −8
Original line number Original line Diff line number Diff line
@@ -33,12 +33,6 @@ struct msm_dsi_phy_cfg { 
	unsigned long	min_pll_rate;

	unsigned long	min_pll_rate;

	unsigned long	max_pll_rate;

	unsigned long	max_pll_rate;





	/*

	 * Each cell {phy_id, pll_id} of the truth table indicates

	 * if the source PLL selection bit should be set for each PHY.

	 * Fill default H/W values in illegal cells, eg. cell {0, 1}.

	 */

	bool src_pll_truthtable[DSI_MAX][DSI_MAX];

	const resource_size_t io_start[DSI_MAX];

	const resource_size_t io_start[DSI_MAX];

	const int num_dsi_phy;

	const int num_dsi_phy;

	const int quirks;

	const int quirks;
@@ -121,7 +115,5 @@ int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, 
				struct msm_dsi_phy_clk_request *clk_req);

				struct msm_dsi_phy_clk_request *clk_req);

int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,

int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,

				struct msm_dsi_phy_clk_request *clk_req);

				struct msm_dsi_phy_clk_request *clk_req);

void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,

				u32 bit_mask);





#endif /* __DSI_PHY_H__ */
 
#endif /* __DSI_PHY_H__ */

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

+0 −2
Original line number Original line Diff line number Diff line
@@ -921,7 +921,6 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy) 
}

}





const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {

const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {

	.src_pll_truthtable = { {false, false}, {true, false} },

	.has_phy_lane = true,

	.has_phy_lane = true,

	.reg_cfg = {

	.reg_cfg = {

		.num = 1,

		.num = 1,
@@ -943,7 +942,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { 
};

};





const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {

const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {

	.src_pll_truthtable = { {false, false}, {true, false} },

	.has_phy_lane = true,

	.has_phy_lane = true,

	.reg_cfg = {

	.reg_cfg = {

		.num = 1,

		.num = 1,

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

+7 −6
Original line number Original line Diff line number Diff line
@@ -947,6 +947,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, 
	int ret;

	int ret;

	void __iomem *base = phy->base;

	void __iomem *base = phy->base;

	void __iomem *lane_base = phy->lane_base;

	void __iomem *lane_base = phy->lane_base;

	u32 glbl_test_ctrl;





	if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {

	if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {

		DRM_DEV_ERROR(&phy->pdev->dev,

		DRM_DEV_ERROR(&phy->pdev->dev,
@@ -994,10 +995,12 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, 
	udelay(100);

	udelay(100);

	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);

	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);





	msm_dsi_phy_set_src_pll(phy, src_pll_id,

	glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);

				REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,

	if (phy->id == DSI_1 && src_pll_id == DSI_0)

				DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);

		glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;



	else

		glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;

	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, glbl_test_ctrl);

	ret = dsi_14nm_set_usecase(phy);

	ret = dsi_14nm_set_usecase(phy);

	if (ret) {

	if (ret) {

		DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",

		DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
@@ -1021,7 +1024,6 @@ static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy) 
}

}





const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {

const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {

	.src_pll_truthtable = { {false, false}, {true, false} },

	.has_phy_lane = true,

	.has_phy_lane = true,

	.reg_cfg = {

	.reg_cfg = {

		.num = 1,

		.num = 1,
@@ -1043,7 +1045,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { 
};

};





const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {

const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {

	.src_pll_truthtable = { {false, false}, {true, false} },

	.has_phy_lane = true,

	.has_phy_lane = true,

	.reg_cfg = {

	.reg_cfg = {

		.num = 1,

		.num = 1,

drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c

+7 −4
Original line number Original line Diff line number Diff line
@@ -70,6 +70,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, 
	int i;

	int i;

	void __iomem *base = phy->base;

	void __iomem *base = phy->base;

	u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};

	u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};

	u32 val;





	DBG("");

	DBG("");
@@ -83,9 +84,12 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, 




	dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);

	dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);





	msm_dsi_phy_set_src_pll(phy, src_pll_id,

	val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);

				REG_DSI_20nm_PHY_GLBL_TEST_CTRL,

	if (src_pll_id == DSI_1)

				DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);

		val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;

	else

		val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;

	dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val);





	for (i = 0; i < 4; i++) {

	for (i = 0; i < 4; i++) {

		dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),

		dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
@@ -125,7 +129,6 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy) 
}

}





const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {

const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {

	.src_pll_truthtable = { {false, true}, {false, true} },

	.has_phy_regulator = true,

	.has_phy_regulator = true,

	.reg_cfg = {

	.reg_cfg = {

		.num = 2,

		.num = 2,