Commit 36a6418b authored by Marc Kleine-Budde's avatar Marc Kleine-Budde
Browse files

Revert "ARM: dts: stm32: add CAN support on stm32f746" 

This reverts commit 0920ccdf.

The commit 0920ccdf ("ARM: dts: stm32: add CAN support on
stm32f746") depends on the patch "dt-bindings: mfd: stm32f7: add
binding definition for CAN3" [1], which is not in net/main, yet. This
results in a parsing error of "stm32f746.dtsi".

So revert this commit.

[1] https://lore.kernel.org/all/20230423172528.1398158-2-dario.binacchi@amarulasolutions.com



Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Cc: Alexandre TORGUE <alexandre.torgue@foss.st.com>
Reported-by: default avatarkernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202305172108.x5acbaQG-lkp@intel.com
Closes: https://lore.kernel.org/oe-kbuild-all/202305172130.eGGEUhpi-lkp@intel.com


Fixes: 0920ccdf ("ARM: dts: stm32: add CAN support on stm32f746")
Suggested-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/20230517181950.1106697-1-mkl@pengutronix.de


Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent c1e4f5a4

arch/arm/boot/dts/stm32f746.dtsi

+0 −47
Original line number Diff line number Diff line
@@ -257,23 +257,6 @@ 
			status = "disabled";

		};



		can3: can@40003400 {

			compatible = "st,stm32f4-bxcan";

			reg = <0x40003400 0x200>;

			interrupts = <104>, <105>, <106>, <107>;

			interrupt-names = "tx", "rx0", "rx1", "sce";

			resets = <&rcc STM32F7_APB1_RESET(CAN3)>;

			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;

			st,gcan = <&gcan3>;

			status = "disabled";

		};



		gcan3: gcan@40003600 {

			compatible = "st,stm32f4-gcan", "syscon";

			reg = <0x40003600 0x200>;

			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;

		};



		usart2: serial@40004400 {

			compatible = "st,stm32f7-uart";

			reg = <0x40004400 0x400>;
@@ -354,36 +337,6 @@ 
			status = "disabled";

		};



		can1: can@40006400 {

			compatible = "st,stm32f4-bxcan";

			reg = <0x40006400 0x200>;

			interrupts = <19>, <20>, <21>, <22>;

			interrupt-names = "tx", "rx0", "rx1", "sce";

			resets = <&rcc STM32F7_APB1_RESET(CAN1)>;

			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;

			st,can-primary;

			st,gcan = <&gcan1>;

			status = "disabled";

		};



		gcan1: gcan@40006600 {

			compatible = "st,stm32f4-gcan", "syscon";

			reg = <0x40006600 0x200>;

			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;

		};



		can2: can@40006800 {

			compatible = "st,stm32f4-bxcan";

			reg = <0x40006800 0x200>;

			interrupts = <63>, <64>, <65>, <66>;

			interrupt-names = "tx", "rx0", "rx1", "sce";

			resets = <&rcc STM32F7_APB1_RESET(CAN2)>;

			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;

			st,can-secondary;

			st,gcan = <&gcan1>;

			status = "disabled";

		};



		cec: cec@40006c00 {

			compatible = "st,stm32-cec";

			reg = <0x40006C00 0x400>;