Commit c1e4f5a4 authored by Marc Kleine-Budde's avatar Marc Kleine-Budde
Browse files

Merge patch series "can: kvaser_pciefd: Bug fixes" 

Jimmy Assarsson <extja@kvaser.com> says:

This patch series contains various bug fixes for the kvaser_pciefd
driver.

Link: https://lore.kernel.org/r/20230516134318.104279-1-extja@kvaser.com


Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parents 6ad85ed0 11164bc3

drivers/net/can/kvaser_pciefd.c

+29 −22
Original line number Diff line number Diff line
@@ -71,10 +71,12 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices"); 
#define KVASER_PCIEFD_SYSID_BUILD_REG (KVASER_PCIEFD_SYSID_BASE + 0x14)

/* Shared receive buffer registers */

#define KVASER_PCIEFD_SRB_BASE 0x1f200

#define KVASER_PCIEFD_SRB_FIFO_LAST_REG (KVASER_PCIEFD_SRB_BASE + 0x1f4)

#define KVASER_PCIEFD_SRB_CMD_REG (KVASER_PCIEFD_SRB_BASE + 0x200)

#define KVASER_PCIEFD_SRB_IEN_REG (KVASER_PCIEFD_SRB_BASE + 0x204)

#define KVASER_PCIEFD_SRB_IRQ_REG (KVASER_PCIEFD_SRB_BASE + 0x20c)

#define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210)

#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG (KVASER_PCIEFD_SRB_BASE + 0x214)

#define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218)

/* EPCS flash controller registers */

#define KVASER_PCIEFD_SPI_BASE 0x1fc00
@@ -111,6 +113,9 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices"); 
/* DMA support */

#define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)



/* SRB current packet level */

#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK 0xff



/* DMA Enable */

#define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
@@ -526,7 +531,7 @@ static int kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can) 
	      KVASER_PCIEFD_KCAN_IRQ_TOF | KVASER_PCIEFD_KCAN_IRQ_ABD |

	      KVASER_PCIEFD_KCAN_IRQ_TAE | KVASER_PCIEFD_KCAN_IRQ_TAL |

	      KVASER_PCIEFD_KCAN_IRQ_FDIC | KVASER_PCIEFD_KCAN_IRQ_BPP |

	      KVASER_PCIEFD_KCAN_IRQ_TAR | KVASER_PCIEFD_KCAN_IRQ_TFD;

	      KVASER_PCIEFD_KCAN_IRQ_TAR;



	iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
@@ -554,6 +559,8 @@ static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can) 


	if (can->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)

		mode |= KVASER_PCIEFD_KCAN_MODE_LOM;

	else

		mode &= ~KVASER_PCIEFD_KCAN_MODE_LOM;



	mode |= KVASER_PCIEFD_KCAN_MODE_EEN;

	mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
@@ -572,7 +579,7 @@ static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can) 


	spin_lock_irqsave(&can->lock, irq);

	iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);

	iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD,

	iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,

		  can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);



	status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
@@ -615,7 +622,7 @@ static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can) 
	iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);

	iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);



	iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD,

	iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,

		  can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);



	mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
@@ -719,6 +726,7 @@ static int kvaser_pciefd_stop(struct net_device *netdev) 
		iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);

		del_timer(&can->bec_poll_timer);

	}

	can->can.state = CAN_STATE_STOPPED;

	close_candev(netdev);



	return ret;
@@ -1007,8 +1015,7 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) 
		SET_NETDEV_DEV(netdev, &pcie->pci->dev);



		iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);

		iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD |

			  KVASER_PCIEFD_KCAN_IRQ_TFD,

		iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,

			  can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);



		pcie->can[i] = can;
@@ -1058,6 +1065,7 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie) 
{

	int i;

	u32 srb_status;

	u32 srb_packet_count;

	dma_addr_t dma_addr[KVASER_PCIEFD_DMA_COUNT];



	/* Disable the DMA */
@@ -1085,6 +1093,15 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie) 
		  KVASER_PCIEFD_SRB_CMD_RDB1,

		  pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);



	/* Empty Rx FIFO */

	srb_packet_count = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG) &

			   KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK;

	while (srb_packet_count) {

		/* Drop current packet in FIFO */

		ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_FIFO_LAST_REG);

		srb_packet_count--;

	}



	srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);

	if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DI)) {

		dev_err(&pcie->pci->dev, "DMA not idle before enabling\n");
@@ -1425,9 +1442,6 @@ static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie, 
		cmd = KVASER_PCIEFD_KCAN_CMD_AT;

		cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;

		iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);



		iowrite32(KVASER_PCIEFD_KCAN_IRQ_TFD,

			  can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);

	} else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET &&

		   p->header[0] & KVASER_PCIEFD_SPACK_IRM &&

		   cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&
@@ -1714,15 +1728,6 @@ static int kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can) 
	if (irq & KVASER_PCIEFD_KCAN_IRQ_TOF)

		netdev_err(can->can.dev, "Tx FIFO overflow\n");



	if (irq & KVASER_PCIEFD_KCAN_IRQ_TFD) {

		u8 count = ioread32(can->reg_base +

				    KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;



		if (count == 0)

			iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,

				  can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);

	}



	if (irq & KVASER_PCIEFD_KCAN_IRQ_BPP)

		netdev_err(can->can.dev,

			   "Fail to change bittiming, when not in reset mode\n");
@@ -1824,6 +1829,11 @@ static int kvaser_pciefd_probe(struct pci_dev *pdev, 
	if (err)

		goto err_teardown_can_ctrls;



	err = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler,

			  IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie);

	if (err)

		goto err_teardown_can_ctrls;



	iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1,

		  pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
@@ -1844,11 +1854,6 @@ static int kvaser_pciefd_probe(struct pci_dev *pdev, 
	iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1,

		  pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);



	err = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler,

			  IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie);

	if (err)

		goto err_teardown_can_ctrls;



	err = kvaser_pciefd_reg_candev(pcie);

	if (err)

		goto err_free_irq;
@@ -1856,6 +1861,8 @@ static int kvaser_pciefd_probe(struct pci_dev *pdev, 
	return 0;



err_free_irq:

	/* Disable PCI interrupts */

	iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);

	free_irq(pcie->pci->irq, pcie);



err_teardown_can_ctrls: