EDAC/i10nm: Make more configurations CPU model specific

mainline inclusion
from mainline-v6.3-rc1
commit dd7814b7
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8Y47N
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=dd7814b78539416c6e561eeaa0951b3e88ac799e



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The numbers of memory controllers per socket, channels per memory
controller, DIMMs per channel and the triples of bus/device/function
of PCI devices used in i10nm_edac can be CPU model specific.
Add new fields to the structure res_config for above numbers and
triples to make them CPU model specific.

Intel-SIG: commit dd7814b7 EDAC/i10nm: Make more configurations CPU model specific.
Backport to provide more information related to CPU model specific for EDAC.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/all/20230113032802.41752-1-qiuxu.zhuo@intel.com


Signed-off-by: Wen Jin <wen.jin@intel.com>