Commit 328141e5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC updates from Ulf Hansson:
 "MMC core:
   - Add support for the asynchronous SDIO wakeup interrupts
   - Skip redundant evaluation of eMMC HS400 caps when no-MMC-cap
   - Add support to store error stats from host drivers
   - Extend debugfs to show error stats from host drivers
   - Add single I/O read support in the recovery path for 4k sector cards

  MMC host:
   - dw_mmc-exynos: Convert corresponding DT bindings to the dtschema
   - dw_mmc-rockchip: Add support for the Rockchip RV1126 variant
   - mmc_spi: Convert corresponding DT bindings to the dtschema
   - mtk-sd: Extend support for interrupts/pinctrls for SDIO low-power mode
   - mtk-sd: Add support for SDIO wake irqs
   - mtk-sd: Add support for the Mediatek MT8188 variant
   - renesas_sdhi: Drop redundant manual tap correction for newer SoCs
   - renesas_sdhi: Add support for the R-Car S4-8 and generic Gen4 variants
   - sdhci/cqhci: Add support to capture stats from host errors
   - sdhci-brcmstb: Add ability to increase max clock rate for SDIO on 72116b0
   - sdhci-msm: Add support for the MSM8998 and SM8450 variant
   - sdhci-of-at91: Fixup UHS-I mode by rewriting of MC1R
   - sdhci-of-dwcmshc: Add support for the Rockchip rk3588 variant
   - sdhci-of-dwcmshc: Enable reset support for the Rockchip variants
   - sdhci-pci-gli: Improve I/O read/write performance for GL9763E
   - sdhci-s3c: Convert corresponding DT bindings to the dtschema
   - tmio: Avoid glitches when resetting

  MEMSTICK core:
   - A couple of minor fixes and cleanups"

* tag 'mmc-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (61 commits)
  mmc: mediatek: add support for SDIO eint wakup IRQ
  mmc: core: Add support for SDIO wakeup interrupt
  dt-bindings: mmc: mtk-sd: extend interrupts and pinctrls properties
  dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
  mmc: renesas_sdhi: newer SoCs don't need manual tap correction
  mmc: cavium-thunderx: Add of_node_put() when breaking out of loop
  mmc: cavium-octeon: Add of_node_put() when breaking out of loop
  mmc: core: quirks: Add of_node_put() when breaking out of loop
  mmc: sdhci-brcmstb: use clk_get_rate(base_clk) in PM resume
  dt-bindings: mmc: sdhci-msm: Document the SM8450 compatible
  mmc: sdhci-msm: drop redundant of_device_id entries
  dt-bindings: mmc: sdhci-msm: add MSM8998
  mmc: block: Add single read for 4k sector cards
  mmc: mxcmmc: Use mmc_card_sdio macro
  mmc: core: Use mmc_card_* macro and add a new for the sd_combo type
  dt-bindings: mmc: sdhci-msm: constrain reg-names per variants
  dt-bindings: mmc: sdhci-msm: fix reg-names entries
  dt-bindings: mmc: Add compatible for MediaTek MT8188
  dt-bindings: mmc: sdhci-msm: document resets
  mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R
  ...
parents eff0cb3d 527f36f5

Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml

+26 −6
Original line number Diff line number Diff line
@@ -10,9 +10,6 @@ maintainers: 
  - Al Cooper <alcooperx@gmail.com>

  - Florian Fainelli <f.fainelli@gmail.com>



allOf:

  - $ref: mmc-controller.yaml#



properties:

  compatible:

    oneOf:
@@ -42,23 +39,46 @@ properties: 
    maxItems: 1



  clocks:

    maxItems: 1

    description:

      handle to core clock for the sdhci controller.

    minItems: 1

    items:

      - description: handle to core clock for the sdhci controller

      - description: handle to improved 150Mhz clock for sdhci controller (Optional clock)



  clock-names:

    minItems: 1

    items:

      - const: sw_sdio

      - const: sdio_freq # Optional clock



  clock-frequency:

    description:

      Maximum operating frequency of sdio_freq sdhci controller clock

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 100000000

    maximum: 150000000



  sdhci,auto-cmd12:

    type: boolean

    description: Specifies that controller should use auto CMD12



allOf:

  - $ref: mmc-controller.yaml#

  - if:

      properties:

        clock-names:

          contains:

            const: sdio_freq



    then:

      required:

        - clock-frequency



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names



unevaluatedProperties: false

Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt

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* Samsung Exynos specific extensions to the Synopsys Designware Mobile

  Storage Host Controller



The Synopsys designware mobile storage host controller is used to interface

a SoC with storage medium such as eMMC or SD/MMC cards. This file documents

differences between the core Synopsys dw mshc controller properties described

by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific

extensions to the Synopsys Designware Mobile Storage Host Controller.



Required Properties:



* compatible: should be

	- "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210

	  specific extensions.

	- "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412

	  specific extensions.

	- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250

	  specific extensions.

	- "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420

	  specific extensions.

	- "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7

	  specific extensions.

	- "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7

	  specific extensions having an SMU.

	- "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific

	  extensions.



* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface

  unit (ciu) clock. This property is applicable only for Exynos5 SoC's and

  ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.



* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value

  in transmit mode and CIU clock phase shift value in receive mode for single

  data rate mode operation. Refer notes below for the order of the cells and the

  valid values.



* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value

  in transmit mode and CIU clock phase shift value in receive mode for double

  data rate mode operation. Refer notes below for the order of the cells and the

  valid values.

* samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase

  shift value for hs400 mode operation.



  Notes for the sdr-timing and ddr-timing values:



    The order of the cells should be

      - First Cell: CIU clock phase shift value for tx mode.

      - Second Cell: CIU clock phase shift value for rx mode.



    Valid values for SDR and DDR CIU clock timing for Exynos5250:

      - valid value for tx phase shift and rx phase shift is 0 to 7.

      - when CIU clock divider value is set to 3, all possible 8 phase shift

        values can be used.

      - if CIU clock divider value is 0 (that is divide by 1), both tx and rx

        phase shift clocks should be 0.



* samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode

  (Latency value for delay line in Read path)



Required properties for a slot (Deprecated - Recommend to use one slot per host):



* gpios: specifies a list of gpios used for command, clock and data bus. The

  first gpio is the command line and the second gpio is the clock line. The

  rest of the gpios (depending on the bus-width property) are the data lines in

  no particular order. The format of the gpio specifier depends on the gpio

  controller.

(Deprecated - Refer to Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt)



Example:



  The MSHC controller node can be split into two portions, SoC specific and

  board specific portions as listed below.



	dwmmc0@12200000 {

		compatible = "samsung,exynos5250-dw-mshc";

		reg = <0x12200000 0x1000>;

		interrupts = <0 75 0>;

		#address-cells = <1>;

		#size-cells = <0>;

	};



	dwmmc0@12200000 {

		cap-mmc-highspeed;

		cap-sd-highspeed;

		broken-cd;

		fifo-depth = <0x80>;

		card-detect-delay = <200>;

		samsung,dw-mshc-ciu-div = <3>;

		samsung,dw-mshc-sdr-timing = <2 3>;

		samsung,dw-mshc-ddr-timing = <1 2>;

		samsung,dw-mshc-hs400-timing = <0 2>;

		samsung,read-strobe-delay = <90>;

		bus-width = <8>;

	};

Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt

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+0 −29
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MMC/SD/SDIO slot directly connected to a SPI bus



This file documents differences between the core properties described

by mmc.txt and the properties used by the mmc_spi driver.



Required properties:

- spi-max-frequency : maximum frequency for this device (Hz).



Optional properties:

- voltage-ranges : two cells are required, first cell specifies minimum

  slot voltage (mV), second cell specifies maximum slot voltage (mV).

  Several ranges could be specified. If not provided, 3.2v..3.4v is assumed.

- gpios : may specify GPIOs in this order: Card-Detect GPIO,

  Write-Protect GPIO. Note that this does not follow the

  binding from mmc.txt, for historical reasons.



Example:



	mmc-slot@0 {

		compatible = "fsl,mpc8323rdb-mmc-slot",

			     "mmc-spi-slot";

		reg = <0>;

		gpios = <&qe_pio_d 14 1

			 &qe_pio_d 15 0>;

		voltage-ranges = <3300 3300>;

		spi-max-frequency = <50000000>;

		interrupts = <42>;

		interrupt-parent = <&PIC>;

	};

Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml

0 → 100644
+77 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mmc/mmc-spi-slot.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MMC/SD/SDIO slot directly connected to a SPI bus



maintainers:

  - Ulf Hansson <ulf.hansson@linaro.org>



allOf:

  - $ref: "mmc-controller.yaml"

  - $ref: /schemas/spi/spi-peripheral-props.yaml



description: |

  The extra properties used by an mmc connected via SPI.



properties:

  compatible:

    const: mmc-spi-slot



  reg:

    maxItems: 1



  spi-max-frequency: true



  interrupts:

    maxItems: 1



  voltage-ranges:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    description: |

      Two cells are required, first cell specifies minimum slot voltage (mV),

      second cell specifies maximum slot voltage (mV).

    items:

      - description: |

          value for minimum slot voltage in mV

        default: 3200

      - description: |

          value for maximum slot voltage in mV

        default: 3400



  gpios:

    description: |

      For historical reasons, this does not follow the generic mmc-controller

      binding.

    minItems: 1

    items:

      - description: Card-Detect GPIO

      - description: Write-Protect GPIO



required:

  - compatible

  - reg

  - spi-max-frequency



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/gpio/gpio.h>

    spi {

      #address-cells = <1>;

      #size-cells = <0>;

      mmc@0 {

        compatible = "mmc-spi-slot";

        reg = <0>;

        gpios = <&gpio 14 GPIO_ACTIVE_LOW>, <&gpio 15 GPIO_ACTIVE_HIGH>;

        voltage-ranges = <3300 3300>;

        spi-max-frequency = <50000000>;

        interrupts = <42>;

        interrupt-parent = <&PIC>;

      };

    };



...

Documentation/devicetree/bindings/mmc/mtk-sd.yaml

+54 −8
Original line number Diff line number Diff line
@@ -30,13 +30,11 @@ properties: 
          - const: mediatek,mt7623-mmc

          - const: mediatek,mt2701-mmc

      - items:

          - const: mediatek,mt8186-mmc

          - const: mediatek,mt8183-mmc

      - items:

          - const: mediatek,mt8192-mmc

          - const: mediatek,mt8183-mmc

      - items:

          - const: mediatek,mt8195-mmc

          - enum:

              - mediatek,mt8186-mmc

              - mediatek,mt8188-mmc

              - mediatek,mt8192-mmc

              - mediatek,mt8195-mmc

          - const: mediatek,mt8183-mmc



  reg:
@@ -72,12 +70,27 @@ properties: 
      - const: ahb_cg



  interrupts:

    maxItems: 1

    description:

      Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended

      interrupt is required and be configured as wakeup source irq.

    minItems: 1

    maxItems: 2



  interrupt-names:

    items:

      - const: msdc

      - const: sdio_wakeup



  pinctrl-names:

    description:

      Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin

      will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this

      scenario.

    minItems: 2

    items:

      - const: default

      - const: state_uhs

      - const: state_eint



  pinctrl-0:

    description:
@@ -89,6 +102,11 @@ properties: 
      should contain uhs mode pin ctrl.

    maxItems: 1



  pinctrl-2:

    description:

      should switch dat1 pin to GPIO mode.

    maxItems: 1



  assigned-clocks:

    description:

      PLL of the source clock.
@@ -208,4 +226,32 @@ examples: 
        mediatek,hs400-cmd-resp-sel-rising;

    };



    mmc3: mmc@11260000 {

        compatible = "mediatek,mt8173-mmc";

        reg = <0x11260000 0x1000>;

        clock-names = "source", "hclk";

        clocks = <&pericfg CLK_PERI_MSDC30_3>,

                 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;

        interrupt-names = "msdc", "sdio_wakeup";

        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,

                     <&pio 23 IRQ_TYPE_LEVEL_LOW>;

        pinctrl-names = "default", "state_uhs", "state_eint";

        pinctrl-0 = <&mmc2_pins_default>;

        pinctrl-1 = <&mmc2_pins_uhs>;

        pinctrl-2 = <&mmc2_pins_eint>;

        bus-width = <4>;

        max-frequency = <200000000>;

        cap-sd-highspeed;

        sd-uhs-sdr104;

        keep-power-in-suspend;

        wakeup-source;

        cap-sdio-irq;

        no-mmc;

        no-sd;

        non-removable;

        vmmc-supply = <&sdio_fixed_3v3>;

        vqmmc-supply = <&mt6397_vgp3_reg>;

        mmc-pwrseq = <&wifi_pwrseq>;

    };



...