Commit 3137f792 authored by Hansen's avatar Hansen Committed by Alex Deucher
Browse files

drm/amd/display: Set phy_mux_sel bit in dmub scratch register 



[Why]
B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or
PHYC/PHY D.

[How]
Based on chip internal hardware revision id determine it is B0 and set
DMUB scratch register so DMUBFW can connect the display pipe is
connected correctly to the dig.

Cc: Wayne Lin <wayne.lin@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarHansen <Hansen.Dsouza@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a9a1ac44

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+1 −1
Original line number Diff line number Diff line
@@ -1825,7 +1825,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) 
		break;

	case IP_VERSION(3, 1, 2):

	case IP_VERSION(3, 1, 3):

		dmub_asic = DMUB_ASIC_DCN31;

		dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;

		fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;

		break;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

+1 −0
Original line number Diff line number Diff line
@@ -97,6 +97,7 @@ enum dmub_asic { 
	DMUB_ASIC_DCN302,

	DMUB_ASIC_DCN303,

	DMUB_ASIC_DCN31,

	DMUB_ASIC_DCN31B,

	DMUB_ASIC_MAX,

};

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

+4 −2
Original line number Diff line number Diff line
@@ -370,8 +370,10 @@ union dmub_fw_boot_options { 
		uint32_t z10_disable: 1; /**< 1 to disable z10 */

		uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */

		uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */

		uint32_t reserved_unreleased2: 1; /**< reserved for an unreleased feature */

		uint32_t root_clock_gating: 1; /**< 1 if all root clock gating is enabled */

		uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */

		uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */

		/**< 1 if all root clock gating is enabled and low power memory is enabled*/

		uint32_t power_optimization: 1;

		uint32_t diag_env: 1; /* 1 if diagnostic environment */



		uint32_t reserved : 19; /**< reserved */

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

+2 −0
Original line number Diff line number Diff line
@@ -340,6 +340,8 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu 
	boot_options.bits.z10_disable = params->disable_z10;

	boot_options.bits.enable_dpia = params->disable_dpia ? 0 : 1;



	boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0;



	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);

}

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

+1 −0
Original line number Diff line number Diff line
@@ -208,6 +208,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 
		break;



	case DMUB_ASIC_DCN31:

	case DMUB_ASIC_DCN31B:

		dmub->regs_dcn31 = &dmub_srv_dcn31_regs;

		funcs->reset = dmub_dcn31_reset;

		funcs->reset_release = dmub_dcn31_reset_release;