Commit a9a1ac44 authored by Martin Leung's avatar Martin Leung Committed by Alex Deucher
Browse files

drm/amd/display: Manually adjust strobe for DCN303 



why:
DCN303's 4 channel SOC BB causes problems at strobe

how:
workaround to manually adjust strobe calculation using FCLK
restrict.

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarAgustin Gutierrez <agustin.gutierrez@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarMartin Leung <Martin.Leung@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e4e330ef

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c

+14 −0
Original line number Diff line number Diff line
@@ -1344,6 +1344,20 @@ void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
			dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz;

			dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz;

		}



		// WA: patch strobe modes to compensate for DCN303 BW issue

		if (dcn3_03_soc.num_chans <= 4) {

			for (i = 0; i < dcn3_03_soc.num_states; i++) {

				if (dcn3_03_soc.clock_limits[i].dram_speed_mts > 1700)

					break;



				if (dcn3_03_soc.clock_limits[i].dram_speed_mts >= 1500) {

					dcn3_03_soc.clock_limits[i].dcfclk_mhz = 100;

					dcn3_03_soc.clock_limits[i].fabricclk_mhz = 100;

				}

			}

		}



		/* re-init DML with updated bb */

		dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);

		if (dc->current_state)