Commit 31033435 authored by Mario Limonciello's avatar Mario Limonciello Committed by Wenkuan Wang
Browse files

x86/CPU/AMD: Add more models to X86_FEATURE_ZEN5 

mainline inclusion
from mainline-v6.8-rc2
commit b9328fd636bd50da89e792e135b234ba8e6fe59f
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I96RWV


CVE: NA

--------------------------------

Add model ranges starting at 0x20, 0x40 and 0x70 to the synthetic
feature flag X86_FEATURE_ZEN5.

Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20240124220749.2983-1-mario.limonciello@amd.com


Signed-off-by: default avatarWenkuan Wang <Wenkuan.Wang@amd.com>
parent 577f33bf

arch/x86/kernel/cpu/amd.c

+3 −0
Original line number Diff line number Diff line
@@ -577,6 +577,9 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 
	case 0x1a:

		switch (c->x86_model) {

		case 0x00 ... 0x0f:

		case 0x20 ... 0x2f:

		case 0x40 ... 0x4f:

		case 0x70 ... 0x7f:

			setup_force_cpu_cap(X86_FEATURE_ZEN5);

			break;

		default: