Commit 308b6b0f authored by Marc Zyngier's avatar Marc Zyngier Committed by Kunkun Jiang
Browse files

arm64: Add RV and RN fields for ESR_ELx_WFx_ISS 

mainline inclusion
from mainline-v5.19-rc1
commit bdcc2f28
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I6YAMV
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bdcc2f280334e4e3f42a5a740494444f1026fb65



-------------------------------

The ISS field exposed by ESR_ELx contain two additional subfields
with FEAT_WFxT:

- RN, the register number containing the timeout
- RV, indicating if the register number is valid

Describe these two fields according to the arch spec.

No functional change.

Reviewed-by: default avatarJoey Gouly <joey.gouly@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220419182755.601427-3-maz@kernel.org


Signed-off-by: default avatarKunkun Jiang <jiangkunkun@huawei.com>
parent af2000e6

arch/arm64/include/asm/esr.h

+2 −0
Original line number Diff line number Diff line
@@ -132,6 +132,8 @@ 
#define ESR_ELx_CV		(UL(1) << 24)

#define ESR_ELx_COND_SHIFT	(20)

#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)

#define ESR_ELx_WFx_ISS_RN	(UL(0x1F) << 5)

#define ESR_ELx_WFx_ISS_RV	(UL(1) << 2)

#define ESR_ELx_WFx_ISS_TI	(UL(3) << 0)

#define ESR_ELx_WFx_ISS_WFxT	(UL(2) << 0)

#define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)