Commit af2000e6 authored by Marc Zyngier's avatar Marc Zyngier Committed by Kunkun Jiang
Browse files

arm64: Expand ESR_ELx_WFx_ISS_TI to match its ARMv8.7 definition 

mainline inclusion
from mainline-v5.19-rc1
commit 6a437208
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I6YAMV
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6a437208cb942a2dd98f7e1c3fd347ed3d425ffc



------------------------------

Starting with FEAT_WFXT in ARMv8.7, the TI field in the ISS
that is reported on a WFx trap is expanded by one bit to
allow the description of WFET and WFIT.

Special care is taken to exclude the WFxT bit from the mask
used to match WFI so that it also matches WFIT when trapped from
EL0.

Reviewed-by: default avatarJoey Gouly <joey.gouly@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220419182755.601427-2-maz@kernel.org


Signed-off-by: default avatarKunkun Jiang <jiangkunkun@huawei.com>
parent 143d2271

arch/arm64/include/asm/esr.h

+4 −2
Original line number Diff line number Diff line
@@ -132,7 +132,8 @@ 
#define ESR_ELx_CV		(UL(1) << 24)

#define ESR_ELx_COND_SHIFT	(20)

#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)

#define ESR_ELx_WFx_ISS_TI	(UL(1) << 0)

#define ESR_ELx_WFx_ISS_TI	(UL(3) << 0)

#define ESR_ELx_WFx_ISS_WFxT	(UL(2) << 0)

#define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)

#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)

#define ESR_ELx_xVC_IMM_MASK	((1UL << 16) - 1)
@@ -145,7 +146,8 @@ 
#define DISR_EL1_ESR_MASK	(ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)



/* ESR value templates for specific events */

#define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)

#define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK |			\

				 (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))

#define ESR_ELx_WFx_WFI_VAL	((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) |	\

				 ESR_ELx_WFx_ISS_WFI)