Commit 2fae03bc authored by Huacai Chen's avatar Huacai Chen Committed by Hongchen Zhang
Browse files

LoongArch: Add writecombine support for drm 

mainline inclusion
from mainline-v5.19-rc1
commit 439057ec
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5OHOB


CVE: NA

--------------------------------

LoongArch maintains cache coherency in hardware, but its WUC attribute
(Weak-ordered UnCached, which is similar to WC) is out of the scope of
cache coherency machanism. This means WUC can only used for write-only
memory regions.

Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: default avatarWANG Xuerui <git@xen0n.name>
Reviewed-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent ce56d4b8

drivers/gpu/drm/drm_vm.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -74,7 +74,7 @@ static pgprot_t drm_io_prot(struct drm_local_map *map, 
	tmp = pgprot_decrypted(tmp);

	tmp = pgprot_decrypted(tmp);





#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || \

#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || \

    defined(__mips__)

    defined(__mips__) || defined(__loongarch__)

	if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING))

	if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING))

		tmp = pgprot_noncached(tmp);

		tmp = pgprot_noncached(tmp);

	else

	else

drivers/gpu/drm/ttm/ttm_bo_util.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -397,7 +397,7 @@ pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp) 
		tmp = pgprot_noncached(tmp);

		tmp = pgprot_noncached(tmp);

#endif

#endif

#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \

#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \

    defined(__powerpc__) || defined(__mips__)

    defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)

	if (caching_flags & TTM_PL_FLAG_WC)

	if (caching_flags & TTM_PL_FLAG_WC)

		tmp = pgprot_writecombine(tmp);

		tmp = pgprot_writecombine(tmp);

	else

	else

include/drm/drm_cache.h

+8 −0
Original line number Original line Diff line number Diff line
@@ -65,6 +65,14 @@ static inline bool drm_arch_can_wc_memory(void) 
	 * optimization entirely for ARM and arm64.

	 * optimization entirely for ARM and arm64.

	 */

	 */

	return false;

	return false;

#elif defined(CONFIG_LOONGARCH)

	/*

	 * LoongArch maintains cache coherency in hardware, but its WUC attribute

	 * (Weak-ordered UnCached, which is similar to WC) is out of the scope of

	 * cache coherency machanism. This means WUC can only used for write-only

	 * memory regions.

	 */

	return false;

#else

#else

	return true;

	return true;

#endif

#endif