LoongArch: Add writecombine support for drm

mainline inclusion
from mainline-v5.19-rc1
commit 439057ec
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5OHOB


CVE: NA

--------------------------------

LoongArch maintains cache coherency in hardware, but its WUC attribute
(Weak-ordered UnCached, which is similar to WC) is out of the scope of
cache coherency machanism. This means WUC can only used for write-only
memory regions.

Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>