Commit 439057ec authored by Huacai Chen's avatar Huacai Chen
Browse files

LoongArch: Add writecombine support for drm



LoongArch maintains cache coherency in hardware, but its WUC attribute
(Weak-ordered UnCached, which is similar to WC) is out of the scope of
cache coherency machanism. This means WUC can only used for write-only
memory regions.

Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: default avatarWANG Xuerui <git@xen0n.name>
Reviewed-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent 08145b08
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+1 −1
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ static pgprot_t drm_io_prot(struct drm_local_map *map,
	pgprot_t tmp = vm_get_page_prot(vma->vm_flags);

#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || \
    defined(__mips__)
    defined(__mips__) || defined(__loongarch__)
	if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING))
		tmp = pgprot_noncached(tmp);
	else
+1 −1
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
#endif /* CONFIG_UML */
#endif /* __i386__ || __x86_64__ */
#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
	defined(__powerpc__) || defined(__mips__)
	defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
	if (caching == ttm_write_combined)
		tmp = pgprot_writecombine(tmp);
	else
+8 −0
Original line number Diff line number Diff line
@@ -67,6 +67,14 @@ static inline bool drm_arch_can_wc_memory(void)
	 * optimization entirely for ARM and arm64.
	 */
	return false;
#elif defined(CONFIG_LOONGARCH)
	/*
	 * LoongArch maintains cache coherency in hardware, but its WUC attribute
	 * (Weak-ordered UnCached, which is similar to WC) is out of the scope of
	 * cache coherency machanism. This means WUC can only used for write-only
	 * memory regions.
	 */
	return false;
#else
	return true;
#endif