EDAC: Add DDR5 new memory type

mainline inclusion
from mainline-v5.11-rc1
commit bc1c99a5
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

Reference: https://git.kernel.org/torvalds/c/bc1c99a5971aa7571e8b9731c28fa32abe12cab8



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commit bc1c99a5 upstream.

Add a new entry to 'enum mem_type' and a new string to
'edac_mem_types[]' for DDR5 new memory type.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
[fix conflict during backport]
Signed-off-by: Pu Wen <puwen@hygon.cn>