Unverified Commit 2ec49273 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'at91-dt-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt 

AT91 DT #2 for 5.16:

- Add DT nodes for TCB and RTC blocks on SAMA7G5
- Add TCB0 for clocksource and clockevent functionality fallback only in
  case PIT64B will fail to probe and as a testbed for this feature on
  the Evaluation Kit.

* tag 'at91-dt-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce
  ARM: dts: at91: sama7g5: add tcb nodes
  ARM: dts: at91: sama7g5: add rtc node

Link: https://lore.kernel.org/r/20211025163428.26285-1-nicolas.ferre@microchip.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 2d3de197 f3c03664

arch/arm/boot/dts/at91-sama7g5ek.dts

+12 −0
Original line number Diff line number Diff line
@@ -654,6 +654,18 @@ 
	status = "okay";

};



&tcb0 {

	timer0: timer@0 {

		compatible = "atmel,tcb-timer";

		reg = <0>;

	};



	timer1: timer@1 {

		compatible = "atmel,tcb-timer";

		reg = <1>;

	};

};



&trng {

	status = "okay";

};

arch/arm/boot/dts/sama7g5.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -130,6 +130,13 @@ 
			reg = <0xe001d060 0x48>;

		};



		rtc: rtc@e001d0a8 {

			compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";

			reg = <0xe001d0a8 0x30>;

			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk32k 1>;

		};



		ps_wdt: watchdog@e001d180 {

			compatible = "microchip,sama7g5-wdt";

			reg = <0xe001d180 0x24>;
@@ -137,6 +144,16 @@ 
			clocks = <&clk32k 0>;

		};



		tcb1: timer@e0800000 {

			compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0xe0800000 0x100>;

			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>;

			clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";

		};



		adc: adc@e1000000 {

			compatible = "microchip,sama7g5-adc";

			reg = <0xe1000000 0x200>;
@@ -454,6 +471,16 @@ 
			status = "disabled";

		};



		tcb0: timer@e2814000 {

			compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0xe2814000 0x100>;

			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>;

			clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";

		};



		flx8: flexcom@e2818000 {

			compatible = "atmel,sama5d2-flexcom";

			reg = <0xe2818000 0x200>;