Commit 2db2fcd7 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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clk: tegra20: Use custom CCLK implementation 



We're going to use the generic cpufreq-dt driver on Tegra20 and thus CCLK
intermediate re-parenting will be performed by the clock driver. There is
now special CCLK implementation that supports all CCLK quirks, this patch
makes Tegra20 SoCs to use that implementation.

Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: default avatarPeter Geis <pgwipeout@gmail.com>
Tested-by: default avatarMarcel Ziswiler <marcel@ziswiler.com>
Tested-by: default avatarJasper Korten <jja2000@gmail.com>
Tested-by: default avatarDavid Heidelberg <david@ixit.cz>
Tested-by: default avatarNicolas Chauvet <kwizart@gmail.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent dec15c99

drivers/clk/tegra/clk-tegra20.c

+5 −2
Original line number Diff line number Diff line
@@ -391,6 +391,8 @@ static struct tegra_clk_pll_params pll_x_params = { 
	.lock_delay = 300,

	.freq_table = pll_x_freq_table,

	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,

	.pre_rate_change = tegra_cclk_pre_pllx_rate_change,

	.post_rate_change = tegra_cclk_post_pllx_rate_change,

};



static struct tegra_clk_pll_params pll_e_params = {
@@ -702,9 +704,10 @@ static void tegra20_super_clk_init(void) 
	struct clk *clk;



	/* CCLK */

	clk = tegra_clk_register_super_mux("cclk", cclk_parents,

	clk = tegra_clk_register_super_cclk("cclk", cclk_parents,

			      ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,

			      clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);

			      clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK,

			      NULL);

	clks[TEGRA20_CLK_CCLK] = clk;



	/* SCLK */