intel_idle: make SPR C1 and C1E be independent

mainline inclusion
from mainline-v6.0
commit 1548fac4
category: bugfix
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I64TXN


CVE: NA

Intel-SIG: commit 1548fac4 intel_idle: make SPR C1 and C1E be independent
Backport for intel_idle c1 and c1e independent support on SPR

--------------------------------

This patch partially reverts the changes made by the following commit:

da0e58c0 intel_idle: add 'preferred_cstates' module argument

As that commit describes, on early Sapphire Rapids Xeon platforms the C1 and
C1E states were mutually exclusive, so that users could only have either C1 and
C6, or C1E and C6.

However, Intel firmware engineers managed to remove this limitation and make C1
and C1E to be completely independent, just like on previous Xeon platforms.

Therefore, this patch:
 * Removes commentary describing the old, and now non-existing SPR C1E
   limitation.
 * Marks SPR C1E as available by default.
 * Removes the 'preferred_cstates' parameter handling for SPR. Both C1 and
   C1E will be available regardless of 'preferred_cstates' value.

We expect that all SPR systems are shipping with new firmware, which includes
the C1/C1E improvement.

Cc: v5.18+ <stable@vger.kernel.org> # v5.18+
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: yingbao jia <yingbao.jia@intel.com>