Commit 2bd4054c authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Jani Nikula
Browse files

drm/i915/display/core: use intel_de_rmw if possible 



The helper makes the code more compact and readable.

Signed-off-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230105131046.2173431-1-andrzej.hajda@intel.com
parent ae2ac2d8

drivers/gpu/drm/i915/display/intel_display.c

+9 −13
Original line number Diff line number Diff line
@@ -201,11 +201,11 @@ static void 
skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)

{

	if (enable)

		intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),

		               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);

		intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),

			     0, DUPS1_GATING_DIS | DUPS2_GATING_DIS);

	else

		intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),

		               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));

		intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),

			     DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0);

}



/* Wa_2006604312:icl,ehl */
@@ -214,11 +214,9 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 
		       bool enable)

{

	if (enable)

		intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),

		               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);

		intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS);

	else

		intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),

		               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);

		intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0);

}



/* Wa_1604331009:icl,jsl,ehl */
@@ -1710,12 +1708,10 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 
	enum transcoder transcoder = crtc_state->cpu_transcoder;

	i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) :

			 CHICKEN_TRANS(transcoder);

	u32 val;



	val = intel_de_read(dev_priv, reg);

	val &= ~HSW_FRAME_START_DELAY_MASK;

	val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1);

	intel_de_write(dev_priv, reg, val);

	intel_de_rmw(dev_priv, reg,

		     HSW_FRAME_START_DELAY_MASK,

		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));

}



static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

+7 −10
Original line number Diff line number Diff line
@@ -649,17 +649,14 @@ static void intel_early_display_was(struct drm_i915_private *i915) 
	 * Also known as Wa_14010480278.

	 */

	if (IS_DISPLAY_VER(i915, 10, 12))

		intel_de_write(i915, GEN9_CLKGATE_DIS_0,

			       intel_de_read(i915, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);

		intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS);



	if (IS_HASWELL(i915)) {

	/*

	 * WaRsPkgCStateDisplayPMReq:hsw

	 * System hang if this isn't done before disabling all planes!

	 */

		intel_de_write(i915, CHICKEN_PAR1_1,

			       intel_de_read(i915, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);

	}

	if (IS_HASWELL(i915))

		intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES);



	if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {

		/* Display WA #1142:kbl,cfl,cml */