Commit 2ab82efe authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2022-03-03' of...

Merge tag 'drm-intel-gt-next-2022-03-03' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

Cross-subsystem Changes:

- drm-next backmerge for buddy allocator changes

Driver Changes:

- Skip i915_perf init for DG2 as it is not yet enabled (Ram)
- Add missing workarounds for DG2 (Clint)
- Add 64K page/align support for platforms like DG2 that require it (Matt A, Ram, Bob)
- Add accelerated migration support for DG2 (Matt A)
- Add flat CCS support for XeHP SDV (Abdiel, Ram)
- Add Compute Command Streamer (CCS) engine support for XeHP SDV (Michel,
  Daniele, Aravind, Matt R)
- Don't support parallel submission on compute / render (Matt B, Matt R)

- Disable i915 build on PREEMPT_RT until RT behaviour fixed (Sebastian)
- Remove RPS interrupt support for TGL+ (Jose)
- Fix S/R with PM_EARLY for non-GTT mappable objects on DG2 (Matt, Lucas)
- Skip stolen memory init if it is fully reserved (Jose)
- Use iosys_map for GuC data structures that may be in LMEM BAR or SMEM (Lucas)
- Do not complain about stale GuC reset notifications for banned contexts (John)

- Move context descriptor fields to intel_lrc.h
- Start adding support for small BAR (Matt A)
- Clarify vma lifetime (Thomas)
- Simplify subplatform detection on TGL (Jose)
- Correct the param count for unset GuC SLPC param (Vinay, Umesh)
- Read RP_STATE_CAP correctly on Gen12 with GuC SLPC (Vinay)
- Initialize GuC submission locks and queues early (Daniele)
- Fix GuC flag query helper function to not modify state (John)

- Drop fake lmem support now we have real hardware available (Lucas)
- Move misplaced W/A to their correct locations (Srinivasan)
- Use get_reset_domain() helper (Tejas)
- Move context descriptor fields to intel_lrc.h (Matt R)
- Selftest improvements (Matt A)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YiBzY1dM7bKwMQ3H@jlahtine-mobl.ger.corp.intel.com
parents c9e9ce0b b2006061
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+1 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ config DRM_I915
	tristate "Intel 8xx/9xx/G3x/G4x/HD Graphics"
	depends on DRM
	depends on X86 && PCI
	depends on !PREEMPT_RT
	select INTEL_GTT
	select INTERVAL_TREE
	# we need shmfs for the swappable backing store, and in particular
+0 −8
Original line number Diff line number Diff line
@@ -19,11 +19,3 @@ config DRM_I915_UNSTABLE
	  Recommended for driver developers _only_.

	  If in the slightest bit of doubt, say "N".

config DRM_I915_UNSTABLE_FAKE_LMEM
	bool "Enable the experimental fake lmem"
	depends on DRM_I915_UNSTABLE
	default n
	help
	  Convert some system memory into a fake local memory region for
	  testing.
+1 −1
Original line number Diff line number Diff line
@@ -1321,7 +1321,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	if (crtc_state->port_clock > 270000) {
		if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
		if (IS_TGL_UY(dev_priv)) {
			return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
						   n_entries);
		} else {
+1 −1
Original line number Diff line number Diff line
@@ -265,7 +265,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
		struct intel_memory_region *mem = obj->mm.region;

		info->apertures->ranges[0].base = mem->io_start;
		info->apertures->ranges[0].size = mem->total;
		info->apertures->ranges[0].size = mem->io_size;

		/* Use fbdev's framebuffer from lmem for discrete */
		info->fix.smem_start =
+10 −0
Original line number Diff line number Diff line
@@ -670,6 +670,16 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
				goto out_err;
			}

			/*
			 * We don't support breadcrumb handshake on these
			 * classes
			 */
			if (siblings[n]->class == RENDER_CLASS ||
			    siblings[n]->class == COMPUTE_CLASS) {
				err = -EINVAL;
				goto out_err;
			}

			if (n) {
				if (prev_engine.engine_class !=
				    ci.engine_class) {
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