Commit 2a50d1a0 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8250: Add GPU speedbin support 



SM8250 has (at least) four GPU speed bins. With the support added on the
driver side, wire up bin detection in the DTS to restrict lower-quality
SKUs from running at frequencies they were not validated at.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony Xperia 5 II (speed bin 0x7)
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230331-topic-konahana_speedbin-v3-5-2dede22dd7f7@linaro.org
parent b53ae6b6

arch/arm64/boot/dts/qcom/sm8250.dtsi

+22 −1
Original line number Diff line number Diff line
@@ -960,6 +960,18 @@ 
			#mbox-cells = <2>;

		};



		qfprom: efuse@784000 {

			compatible = "qcom,sm8250-qfprom", "qcom,qfprom";

			reg = <0 0x00784000 0 0x8ff>;

			#address-cells = <1>;

			#size-cells = <1>;



			gpu_speed_bin: gpu_speed_bin@19b {

				reg = <0x19b 0x1>;

				bits = <5 3>;

			};

		};



		rng: rng@793000 {

			compatible = "qcom,prng-ee";

			reg = <0 0x00793000 0 0x1000>;
@@ -2550,49 +2562,58 @@ 


			qcom,gmu = <&gmu>;



			nvmem-cells = <&gpu_speed_bin>;

			nvmem-cell-names = "speed_bin";



			status = "disabled";



			zap-shader {

				memory-region = <&gpu_mem>;

			};



			/* note: downstream checks gpu binning for 670 Mhz */

			gpu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-670000000 {

					opp-hz = /bits/ 64 <670000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

					opp-supported-hw = <0xa>;

				};



				opp-587000000 {

					opp-hz = /bits/ 64 <587000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;

					opp-supported-hw = <0xb>;

				};



				opp-525000000 {

					opp-hz = /bits/ 64 <525000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;

					opp-supported-hw = <0xf>;

				};



				opp-490000000 {

					opp-hz = /bits/ 64 <490000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

					opp-supported-hw = <0xf>;

				};



				opp-441600000 {

					opp-hz = /bits/ 64 <441600000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;

					opp-supported-hw = <0xf>;

				};



				opp-400000000 {

					opp-hz = /bits/ 64 <400000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

					opp-supported-hw = <0xf>;

				};



				opp-305000000 {

					opp-hz = /bits/ 64 <305000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

					opp-supported-hw = <0xf>;

				};

			};

		};