Commit b53ae6b6 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
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arm64: dts: qcom: sm8150: Add GPU speedbin support 



SM8150 has (at least) two GPU speed bins. With the support added on the
driver side, wire up bin detection in the DTS to restrict lower-quality
SKUs from running at frequencies they were not validated at.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony Xperia 5 (speed bin 0x3)
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230331-topic-konahana_speedbin-v3-4-2dede22dd7f7@linaro.org
parent 1642ab96

arch/arm64/boot/dts/qcom/sm8150.dtsi

+20 −1
Original line number Diff line number Diff line
@@ -950,6 +950,17 @@ 
			status = "disabled";

		};



		qfprom: efuse@784000 {

			compatible = "qcom,sm8150-qfprom", "qcom,qfprom";

			reg = <0 0x00784000 0 0x8ff>;

			#address-cells = <1>;

			#size-cells = <1>;



			gpu_speed_bin: gpu_speed_bin@133 {

				reg = <0x133 0x1>;

				bits = <5 3>;

			};

		};



		qupv3_id_0: geniqup@8c0000 {

			compatible = "qcom,geni-se-qup";
@@ -2165,44 +2176,52 @@ 


			qcom,gmu = <&gmu>;



			nvmem-cells = <&gpu_speed_bin>;

			nvmem-cell-names = "speed_bin";



			status = "disabled";



			zap-shader {

				memory-region = <&gpu_mem>;

			};



			/* note: downstream checks gpu binning for 675 Mhz */

			gpu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-675000000 {

					opp-hz = /bits/ 64 <675000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

					opp-supported-hw = <0x2>;

				};



				opp-585000000 {

					opp-hz = /bits/ 64 <585000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;

					opp-supported-hw = <0x3>;

				};



				opp-499200000 {

					opp-hz = /bits/ 64 <499200000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;

					opp-supported-hw = <0x3>;

				};



				opp-427000000 {

					opp-hz = /bits/ 64 <427000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

					opp-supported-hw = <0x3>;

				};



				opp-345000000 {

					opp-hz = /bits/ 64 <345000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

					opp-supported-hw = <0x3>;

				};



				opp-257000000 {

					opp-hz = /bits/ 64 <257000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

					opp-supported-hw = <0x3>;

				};

			};

		};