Commit 29db30c4 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: rzg2l: Simplify multiplication/shift logic 



"a * (1 << b)" == "a << b".

No change in generated code.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/71e1cf2e30fb2d7966fc8ec6bab23eb7e24aa1c4.1645460687.git.geert+renesas@glider.be
parent 9d18f81b

drivers/clk/renesas/rzg2l-cpg.c

+1 −1
Original line number Diff line number Diff line
@@ -289,7 +289,7 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, 
	val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));

	val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));

	mult = MDIV(val1) + KDIV(val1) / 65536;

	div = PDIV(val1) * (1 << SDIV(val2));

	div = PDIV(val1) << SDIV(val2);



	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);

}