Commit 9d18f81b authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a77995: Add RPC clocks 



Describe the various clocks used by the SPI Multi I/O Bus Controller
(RPC-IF) on the R-Car D3 SoC: RPCSRC internal clock, RPC{,D2} clocks
derived from it, and RPC-IF module clock.

The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
E3, but uses a different pre-divider for the PLL0 parent.  Add a new
macro to describe it, reusing the existing clock type for R-Car E3.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/3fd1e886b7737cd0e199603bae81d01be9dcf3aa.1648546700.git.geert+renesas@glider.be
parent 2a214607

drivers/clk/renesas/r8a77995-cpg-mssr.c

+9 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ enum clk_ids { 
	CLK_S2,

	CLK_S3,

	CLK_SDSRC,

	CLK_RPCSRC,

	CLK_RINT,

	CLK_OCO,
@@ -70,6 +71,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { 
	DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),

	DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),



	DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),



	DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),



	DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
@@ -106,6 +109,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { 
	DEF_GEN3_SDH("sd0h",   R8A77995_CLK_SD0H, CLK_SDSRC,         0x268),

	DEF_GEN3_SD("sd0",     R8A77995_CLK_SD0,  R8A77995_CLK_SD0H, 0x268),



	DEF_BASE("rpc",		R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC,

		 CLK_RPCSRC),

	DEF_BASE("rpcd2",	R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,

		 R8A77995_CLK_RPC),



	DEF_DIV6P1("canfd",    R8A77995_CLK_CANFD, CLK_PLL0D3,    0x244),

	DEF_DIV6P1("mso",      R8A77995_CLK_MSO,   CLK_PLL1D2,    0x014),
@@ -174,6 +182,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { 
	DEF_MOD("can-fd",		 914,	R8A77995_CLK_S3D2),

	DEF_MOD("can-if1",		 915,	R8A77995_CLK_S3D4),

	DEF_MOD("can-if0",		 916,	R8A77995_CLK_S3D4),

	DEF_MOD("rpc-if",		 917,	R8A77995_CLK_RPCD2),

	DEF_MOD("i2c3",			 928,	R8A77995_CLK_S3D2),

	DEF_MOD("i2c2",			 929,	R8A77995_CLK_S3D2),

	DEF_MOD("i2c1",			 930,	R8A77995_CLK_S3D2),

drivers/clk/renesas/rcar-gen3-cpg.h

+4 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ enum rcar_gen3_clk_types { 
	CLK_TYPE_GEN3_OSC,	/* OSC EXTAL predivider and fixed divider */

	CLK_TYPE_GEN3_RCKSEL,	/* Select parent/divider using RCKCR.CKSEL */

	CLK_TYPE_GEN3_RPCSRC,

	CLK_TYPE_GEN3_E3_RPCSRC,

	CLK_TYPE_GEN3_E3_RPCSRC,/* Select parent/divider using RPCCKCR.DIV */

	CLK_TYPE_GEN3_RPC,

	CLK_TYPE_GEN3_RPCD2,
@@ -62,6 +62,9 @@ enum rcar_gen3_clk_types { 
#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1)	\

	DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC,	\

		 (_parent0) << 16 | (_parent1), .div = 8)

#define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1)	\

	DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC,	\

		 (_parent0) << 16 | (_parent1), .div = 5)



struct rcar_gen3_cpg_pll_config {

	u8 extal_div;