Commit 2958d17a authored by Hariprasad Kelam's avatar Hariprasad Kelam Committed by David S. Miller
Browse files

octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon 



Add support for ptp 1-step mode using timecounter. The seconds and
nanoseconds to be updated in PTP header are calculated by adding the
timecounter offset to the free running PTP clock counter time. The PF
driver periodically gets the PTP clock time using AF mbox. The 1-step
support uses HW feature to update correction field rather than
OriginTimestamp field in PTP header.

Signed-off-by: default avatarHariprasad Kelam <hkelam@marvell.com>
Signed-off-by: default avatarNaveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: default avatarSunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a8025e79

drivers/net/ethernet/marvell/octeontx2/af/rpm.c

+17 −2
Original line number Diff line number Diff line
@@ -415,11 +415,26 @@ void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable) 
		return;



	cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_CFG);

	if (enable)

	if (enable) {

		cfg |= RPMX_RX_TS_PREPEND;

	else

		cfg |= RPMX_TX_PTP_1S_SUPPORT;

	} else {

		cfg &= ~RPMX_RX_TS_PREPEND;

		cfg &= ~RPMX_TX_PTP_1S_SUPPORT;

	}



	rpm_write(rpm, lmac_id, RPMX_CMRX_CFG, cfg);



	cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_XIF_MODE);



	if (enable) {

		cfg |= RPMX_ONESTEP_ENABLE;

		cfg &= ~RPMX_TS_BINARY_MODE;

	} else {

		cfg &= ~RPMX_ONESTEP_ENABLE;

	}



	rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_XIF_MODE, cfg);

}



int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 pfc_en)

drivers/net/ethernet/marvell/octeontx2/af/rpm.h

+5 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
/* Registers */

#define RPMX_CMRX_CFG			0x00

#define RPMX_RX_TS_PREPEND              BIT_ULL(22)

#define RPMX_TX_PTP_1S_SUPPORT          BIT_ULL(17)

#define RPMX_CMRX_SW_INT                0x180

#define RPMX_CMRX_SW_INT_W1S            0x188

#define RPMX_CMRX_SW_INT_ENA_W1S        0x198
@@ -72,6 +73,10 @@ 
#define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA		0x8108

#define RPM_DEFAULT_PAUSE_TIME                          0x7FF



#define RPMX_MTI_MAC100X_XIF_MODE		        0x8100

#define RPMX_ONESTEP_ENABLE				BIT_ULL(5)

#define RPMX_TS_BINARY_MODE				BIT_ULL(11)



/* Function Declarations */

int rpm_get_nr_lmacs(void *rpmd);

u8 rpm_get_lmac_type(void *rpmd, int lmac_id);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

+7 −1
Original line number Diff line number Diff line
@@ -4296,8 +4296,14 @@ static int rvu_nix_block_init(struct rvu *rvu, struct nix_hw *nix_hw) 
	/* Restore CINT timer delay to HW reset values */

	rvu_write64(rvu, blkaddr, NIX_AF_CINT_DELAY, 0x0ULL);



	cfg = rvu_read64(rvu, blkaddr, NIX_AF_SEB_CFG);



	/* For better performance use NDC TX instead of NDC RX for SQ's SQEs" */

	rvu_write64(rvu, blkaddr, NIX_AF_SEB_CFG, 0x1ULL);

	cfg |= 1ULL;

	if (!is_rvu_otx2(rvu))

		cfg |= NIX_PTP_1STEP_EN;



	rvu_write64(rvu, blkaddr, NIX_AF_SEB_CFG, cfg);



	if (is_block_implemented(hw, blkaddr)) {

		err = nix_setup_txschq(rvu, nix_hw, blkaddr);

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -266,6 +266,7 @@ 
#define NIX_AF_TX_NPC_CAPTURE_CONFIG	(0x0660)

#define NIX_AF_TX_NPC_CAPTURE_INFO	(0x0670)

#define NIX_AF_SEB_CFG			(0x05F0)

#define NIX_PTP_1STEP_EN		BIT_ULL(2)



#define NIX_AF_DEBUG_NPC_RESP_DATAX(a)          (0x680 | (a) << 3)

#define NIX_AF_SMQX_CFG(a)                      (0x700 | (a) << 16)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

+13 −0
Original line number Diff line number Diff line
@@ -243,6 +243,7 @@ struct otx2_hw { 
#define CN10K_MBOX		1

#define CN10K_LMTST		2

#define CN10K_RPM		3

#define CN10K_PTP_ONESTEP	4

	unsigned long		cap_flag;



#define LMT_LINE_SIZE		128
@@ -276,6 +277,13 @@ struct refill_work { 
	struct otx2_nic *pf;

};



/* PTPv2 originTimestamp structure */

struct ptpv2_tstamp {

	__be16 seconds_msb; /* 16 bits + */

	__be32 seconds_lsb; /* 32 bits = 48 bits*/

	__be32 nanoseconds;

} __packed;



struct otx2_ptp {

	struct ptp_clock_info ptp_info;

	struct ptp_clock *ptp_clock;
@@ -291,6 +299,9 @@ struct otx2_ptp { 
	struct ptp_pin_desc extts_config;

	u64 (*convert_rx_ptp_tstmp)(u64 timestamp);

	u64 (*convert_tx_ptp_tstmp)(u64 timestamp);

	struct delayed_work synctstamp_work;

	u64 tstamp;

	u32 base_ns;

};



#define OTX2_HW_TIMESTAMP_LEN	8
@@ -363,6 +374,7 @@ struct otx2_nic { 
#define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED	BIT_ULL(12)

#define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED	BIT_ULL(13)

#define OTX2_FLAG_DMACFLTR_SUPPORT		BIT_ULL(14)

#define OTX2_FLAG_PTP_ONESTEP_SYNC		BIT_ULL(15)

#define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16)

	u64			flags;

	u64			*cq_op_addr;
@@ -494,6 +506,7 @@ static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 
		__set_bit(CN10K_MBOX, &hw->cap_flag);

		__set_bit(CN10K_LMTST, &hw->cap_flag);

		__set_bit(CN10K_RPM, &hw->cap_flag);

		__set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag);

	}

}