Commit 29364930 authored by Pawan Gupta's avatar Pawan Gupta Committed by Borislav Petkov
Browse files

x86/tsx: Clear CPUID bits when TSX always force aborts 



As a result of TSX deprecation, some processors always abort TSX
transactions by default after a microcode update.

When TSX feature cannot be used it is better to hide it. Clear CPUID.RTM
and CPUID.HLE bits when TSX transactions always abort.

 [ bp: Massage commit message and comments. ]

Signed-off-by: default avatarPawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Reviewed-by: default avatarTony Luck <tony.luck@intel.com>
Tested-by: default avatarNeelima Krishnan <neelima.krishnan@intel.com>
Link: https://lkml.kernel.org/r/5209b3d72ffe5bd3cafdcc803f5b883f785329c3.1623704845.git-series.pawan.kumar.gupta@linux.intel.com
parent ad3c2e17

arch/x86/kernel/cpu/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ extern const struct cpu_dev *const __x86_cpu_dev_start[], 
enum tsx_ctrl_states {

	TSX_CTRL_ENABLE,

	TSX_CTRL_DISABLE,

	TSX_CTRL_RTM_ALWAYS_ABORT,

	TSX_CTRL_NOT_SUPPORTED,

};
@@ -56,6 +57,7 @@ extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state; 
extern void __init tsx_init(void);

extern void tsx_enable(void);

extern void tsx_disable(void);

extern void tsx_clear_cpuid(void);

#else

static inline void tsx_init(void) { }

#endif /* CONFIG_CPU_SUP_INTEL */

arch/x86/kernel/cpu/intel.c

+3 −1
Original line number Diff line number Diff line
@@ -717,8 +717,10 @@ static void init_intel(struct cpuinfo_x86 *c) 


	if (tsx_ctrl_state == TSX_CTRL_ENABLE)

		tsx_enable();

	if (tsx_ctrl_state == TSX_CTRL_DISABLE)

	else if (tsx_ctrl_state == TSX_CTRL_DISABLE)

		tsx_disable();

	else if (tsx_ctrl_state == TSX_CTRL_RTM_ALWAYS_ABORT)

		tsx_clear_cpuid();



	split_lock_init();

	bus_lock_init();

arch/x86/kernel/cpu/tsx.c

+35 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * Intel Transactional Synchronization Extensions (TSX) control.

 *

 * Copyright (C) 2019 Intel Corporation

 * Copyright (C) 2019-2021 Intel Corporation

 *

 * Author:

 *	Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
@@ -84,13 +84,46 @@ static enum tsx_ctrl_states x86_get_tsx_auto_mode(void) 
	return TSX_CTRL_ENABLE;

}



void tsx_clear_cpuid(void)

{

	u64 msr;



	/*

	 * MSR_TFA_TSX_CPUID_CLEAR bit is only present when both CPUID

	 * bits RTM_ALWAYS_ABORT and TSX_FORCE_ABORT are present.

	 */

	if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) &&

	    boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {

		rdmsrl(MSR_TSX_FORCE_ABORT, msr);

		msr |= MSR_TFA_TSX_CPUID_CLEAR;

		wrmsrl(MSR_TSX_FORCE_ABORT, msr);

	}

}



void __init tsx_init(void)

{

	char arg[5] = {};

	int ret;



	if (!tsx_ctrl_is_supported())

	/*

	 * Hardware will always abort a TSX transaction if both CPUID bits

	 * RTM_ALWAYS_ABORT and TSX_FORCE_ABORT are set. In this case, it is

	 * better not to enumerate CPUID.RTM and CPUID.HLE bits. Clear them

	 * here.

	 */

	if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) &&

	    boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {

		tsx_ctrl_state = TSX_CTRL_RTM_ALWAYS_ABORT;

		tsx_clear_cpuid();

		setup_clear_cpu_cap(X86_FEATURE_RTM);

		setup_clear_cpu_cap(X86_FEATURE_HLE);

		return;

	}



	if (!tsx_ctrl_is_supported()) {

		tsx_ctrl_state = TSX_CTRL_NOT_SUPPORTED;

		return;

	}



	ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));

	if (ret >= 0) {