Commit 29288bab authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Matthias Brugger
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arm64: dts: mt8192: Add complete CPU caches information 



This SoC features two clusters composed of:
 - 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative,
                  per-cpu 128KB L2 cache, 4-way set associative;
 - 4x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative,
                  per-cpu 256KB L2 cache, 8-way set associative;
Moreover, the two clusters are sharing a DSU L3 cache with size 2MB,
16-way set associative.

With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221206112330.78431-3-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent b68188a7

arch/arm64/boot/dts/mediatek/mt8192.dtsi

+58 −0
Original line number Diff line number Diff line
@@ -63,6 +63,12 @@ 
			enable-method = "psci";

			clock-frequency = <1701000000>;

			cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			capacity-dmips-mhz = <530>;

		};
@@ -74,6 +80,12 @@ 
			enable-method = "psci";

			clock-frequency = <1701000000>;

			cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			capacity-dmips-mhz = <530>;

		};
@@ -85,6 +97,12 @@ 
			enable-method = "psci";

			clock-frequency = <1701000000>;

			cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			capacity-dmips-mhz = <530>;

		};
@@ -96,6 +114,12 @@ 
			enable-method = "psci";

			clock-frequency = <1701000000>;

			cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			capacity-dmips-mhz = <530>;

		};
@@ -107,6 +131,12 @@ 
			enable-method = "psci";

			clock-frequency = <2171000000>;

			cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;

			i-cache-size = <65536>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			capacity-dmips-mhz = <1024>;

		};
@@ -118,6 +148,12 @@ 
			enable-method = "psci";

			clock-frequency = <2171000000>;

			cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;

			i-cache-size = <65536>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			capacity-dmips-mhz = <1024>;

		};
@@ -129,6 +165,12 @@ 
			enable-method = "psci";

			clock-frequency = <2171000000>;

			cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;

			i-cache-size = <65536>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			capacity-dmips-mhz = <1024>;

		};
@@ -140,6 +182,12 @@ 
			enable-method = "psci";

			clock-frequency = <2171000000>;

			cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;

			i-cache-size = <65536>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			capacity-dmips-mhz = <1024>;

		};
@@ -179,18 +227,28 @@ 
		l2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-size = <131072>;

			cache-line-size = <64>;

			cache-sets = <512>;

			next-level-cache = <&l3_0>;

		};



		l2_1: l2-cache1 {

			compatible = "cache";

			cache-level = <2>;

			cache-size = <262144>;

			cache-line-size = <64>;

			cache-sets = <512>;

			next-level-cache = <&l3_0>;

		};



		l3_0: l3-cache {

			compatible = "cache";

			cache-level = <3>;

			cache-size = <2097152>;

			cache-line-size = <64>;

			cache-sets = <2048>;

			cache-unified;

		};



		idle-states {