Commit b68188a7 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Matthias Brugger
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arm64: dts: mt8195: Add complete CPU caches information 



This SoC features two clusters composed of:
 - 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative,
                  per-cpu 128KB L2 cache, 4-way set associative;
 - 4x Cortex A78: 64KB I-cache and 64KB D-cache, 4-way set associative,
                  per-cpu 256KB L2 cache, 8-way set associative;
Moreover, the two clusters are sharing a DSU L3 cache with size 2MB,
16-way set associative.

With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221206112330.78431-2-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent a89897e5

arch/arm64/boot/dts/mediatek/mt8195.dtsi

+58 −0
Original line number Diff line number Diff line
@@ -39,6 +39,12 @@ 
			clock-frequency = <1701000000>;

			capacity-dmips-mhz = <308>;

			cpu-idle-states = <&cpu_off_l &cluster_off_l>;

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

		};
@@ -52,6 +58,12 @@ 
			clock-frequency = <1701000000>;

			capacity-dmips-mhz = <308>;

			cpu-idle-states = <&cpu_off_l &cluster_off_l>;

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

		};
@@ -65,6 +77,12 @@ 
			clock-frequency = <1701000000>;

			capacity-dmips-mhz = <308>;

			cpu-idle-states = <&cpu_off_l &cluster_off_l>;

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

		};
@@ -78,6 +96,12 @@ 
			clock-frequency = <1701000000>;

			capacity-dmips-mhz = <308>;

			cpu-idle-states = <&cpu_off_l &cluster_off_l>;

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

		};
@@ -91,6 +115,12 @@ 
			clock-frequency = <2171000000>;

			capacity-dmips-mhz = <1024>;

			cpu-idle-states = <&cpu_off_b &cluster_off_b>;

			i-cache-size = <65536>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			#cooling-cells = <2>;

		};
@@ -104,6 +134,12 @@ 
			clock-frequency = <2171000000>;

			capacity-dmips-mhz = <1024>;

			cpu-idle-states = <&cpu_off_b &cluster_off_b>;

			i-cache-size = <65536>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			#cooling-cells = <2>;

		};
@@ -117,6 +153,12 @@ 
			clock-frequency = <2171000000>;

			capacity-dmips-mhz = <1024>;

			cpu-idle-states = <&cpu_off_b &cluster_off_b>;

			i-cache-size = <65536>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			#cooling-cells = <2>;

		};
@@ -130,6 +172,12 @@ 
			clock-frequency = <2171000000>;

			capacity-dmips-mhz = <1024>;

			cpu-idle-states = <&cpu_off_b &cluster_off_b>;

			i-cache-size = <65536>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			#cooling-cells = <2>;

		};
@@ -215,18 +263,28 @@ 
		l2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-size = <131072>;

			cache-line-size = <64>;

			cache-sets = <512>;

			next-level-cache = <&l3_0>;

		};



		l2_1: l2-cache1 {

			compatible = "cache";

			cache-level = <2>;

			cache-size = <262144>;

			cache-line-size = <64>;

			cache-sets = <512>;

			next-level-cache = <&l3_0>;

		};



		l3_0: l3-cache {

			compatible = "cache";

			cache-level = <3>;

			cache-size = <2097152>;

			cache-line-size = <64>;

			cache-sets = <2048>;

			cache-unified;

		};

	};