Commit 28f81858 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

dt-bindings: memory: lpddr3: convert to dtschema 



Convert the LPDDR3 memory bindings to DT schema format.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: default avatarDmitry Osipenko <digetx@gmail.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220206135807.211767-4-krzysztof.kozlowski@canonical.com
parent 180a276c

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: LPDDR3 SDRAM compliant to JEDEC JESD209-3



maintainers:

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>



properties:

  compatible:

    items:

      - enum:

          - samsung,K3QF2F20DB

      - const: jedec,lpddr3



  '#address-cells':

    const: 1



  density:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Density in megabits of SDRAM chip.

    enum:

      - 4096

      - 8192

      - 16384

      - 32768



  io-width:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      IO bus width in bits of SDRAM chip.

    enum:

      - 64

      - 32

      - 16

      - 8



  manufacturer-id:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Manufacturer ID value read from Mode Register 5.



  revision-id:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    minItems: 2

    maxItems: 2

    items:

      maximum: 255

    description: |

      Revision value of SDRAM chip read from Mode Registers 6 and 7.



  '#size-cells':

    const: 0



  tCKE-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      CKE minimum pulse width (HIGH and LOW pulse width) in terms of number

      of clock cycles.



  tCKESR-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      CKE minimum pulse width during SELF REFRESH (low pulse width during

      SELF REFRESH) in terms of number of clock cycles.



  tDQSCK-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      DQS output data access time from CK_t/CK_c in terms of number of clock

      cycles.



  tFAW-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 63

    description: |

      Four-bank activate window in terms of number of clock cycles.



  tMRD-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Mode register set command delay in terms of number of clock cycles.



  tR2R-C2C-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]

    description: |

      Additional READ-to-READ delay in chip-to-chip cases in terms of number

      of clock cycles.



  tRAS-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 63

    description: |

      Row active time in terms of number of clock cycles.



  tRC-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 63

    description: |

      ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.



  tRCD-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      RAS-to-CAS delay in terms of number of clock cycles.



  tRFC-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 255

    description: |

      Refresh Cycle time in terms of number of clock cycles.



  tRL-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

     READ data latency in terms of number of clock cycles.



  tRPab-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Row precharge time (all banks) in terms of number of clock cycles.



  tRPpb-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Row precharge time (single banks) in terms of number of clock cycles.



  tRRD-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Active bank A to active bank B in terms of number of clock cycles.



  tRTP-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Internal READ to PRECHARGE command delay in terms of number of clock

      cycles.



  tW2W-C2C-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]

    description: |

      Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number

      of clock cycles.



  tWL-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      WRITE data latency in terms of number of clock cycles.



  tWR-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      WRITE recovery time in terms of number of clock cycles.



  tWTR-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Internal WRITE-to-READ command delay in terms of number of clock cycles.



  tXP-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 255

    description: |

      Exit power-down to next valid command delay in terms of number of clock

      cycles.



  tXSR-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 1023

    description: |

      SELF REFRESH exit to next valid command delay in terms of number of clock

      cycles.



patternProperties:

  "^timings@[0-9a-f]+$":

    $ref: jedec,lpddr3-timings.yaml

    description: |

      The lpddr3 node may have one or more child nodes with timings.

      Each timing node provides AC timing parameters of the device for a given

      speed-bin. The user may provide the timings for as many speed-bins as is

      required.



required:

  - compatible

  - '#address-cells'

  - density

  - io-width

  - '#size-cells'



additionalProperties: false



examples:

  - |

    lpddr3 {

        compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";

        density = <16384>;

        io-width = <32>;

        #address-cells = <1>;

        #size-cells = <0>;



        tCKE-min-tck = <2>;

        tCKESR-min-tck = <2>;

        tDQSCK-min-tck = <5>;

        tFAW-min-tck = <5>;

        tMRD-min-tck = <5>;

        tR2R-C2C-min-tck = <0>;

        tRAS-min-tck = <5>;

        tRC-min-tck = <6>;

        tRCD-min-tck = <3>;

        tRFC-min-tck = <17>;

        tRL-min-tck = <14>;

        tRPab-min-tck = <2>;

        tRPpb-min-tck = <2>;

        tRRD-min-tck = <2>;

        tRTP-min-tck = <2>;

        tW2W-C2C-min-tck = <0>;

        tWL-min-tck = <8>;

        tWR-min-tck = <7>;

        tWTR-min-tck = <2>;

        tXP-min-tck = <2>;

        tXSR-min-tck = <12>;



        timings@800000000 {

            compatible = "jedec,lpddr3-timings";

            reg = <800000000>;

            min-freq = <100000000>;

            tCKE = <3750>;

            tCKESR = <3750>;

            tFAW = <25000>;

            tMRD = <7000>;

            tR2R-C2C = <0>;

            tRAS = <23000>;

            tRC = <33750>;

            tRCD = <10000>;

            tRFC = <65000>;

            tRPab = <12000>;

            tRPpb = <12000>;

            tRRD = <6000>;

            tRTP = <3750>;

            tW2W-C2C = <0>;

            tWR = <7500>;

            tWTR = <3750>;

            tXP = <3750>;

            tXSR = <70000>;

        };

    };

Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt

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* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C



Required properties:

- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".

  Example "<vendor>,<type>" values:

    "samsung,K3QF2F20DB"



- density  : <u32> representing density in Mb (Mega bits)

- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64

- #address-cells: Must be set to 1

- #size-cells: Must be set to 0



Optional properties:



- manufacturer-id : <u32>     Manufacturer ID value read from Mode Register 5

- revision-id     : <u32 u32> Revision IDs read from Mode Registers 6 and 7



The following optional properties represent the minimum value of some AC

timing parameters of the DDR device in terms of number of clock cycles.

These values shall be obtained from the device data-sheet.

- tRFC-min-tck

- tRRD-min-tck

- tRPab-min-tck

- tRPpb-min-tck

- tRCD-min-tck

- tRC-min-tck

- tRAS-min-tck

- tWTR-min-tck

- tWR-min-tck

- tRTP-min-tck

- tW2W-C2C-min-tck

- tR2R-C2C-min-tck

- tWL-min-tck

- tDQSCK-min-tck

- tRL-min-tck

- tFAW-min-tck

- tXSR-min-tck

- tXP-min-tck

- tCKE-min-tck

- tCKESR-min-tck

- tMRD-min-tck



Child nodes:

- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".

  "lpddr3-timings" provides AC timing parameters of the device for

  a given speed-bin. Please see

  Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt

  for more information on "lpddr3-timings"



Example:



samsung_K3QF2F20DB: lpddr3 {

	compatible	= "samsung,K3QF2F20DB", "jedec,lpddr3";

	density		= <16384>;

	io-width	= <32>;

	manufacturer-id = <1>;

	revision-id     = <123 234>;

	#address-cells	= <1>;

	#size-cells	= <0>;



	tRFC-min-tck		= <17>;

	tRRD-min-tck		= <2>;

	tRPab-min-tck		= <2>;

	tRPpb-min-tck		= <2>;

	tRCD-min-tck		= <3>;

	tRC-min-tck		= <6>;

	tRAS-min-tck		= <5>;

	tWTR-min-tck		= <2>;

	tWR-min-tck		= <7>;

	tRTP-min-tck		= <2>;

	tW2W-C2C-min-tck	= <0>;

	tR2R-C2C-min-tck	= <0>;

	tWL-min-tck		= <8>;

	tDQSCK-min-tck		= <5>;

	tRL-min-tck		= <14>;

	tFAW-min-tck		= <5>;

	tXSR-min-tck		= <12>;

	tXP-min-tck		= <2>;

	tCKE-min-tck		= <2>;

	tCKESR-min-tck		= <2>;

	tMRD-min-tck		= <5>;



	timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {

		compatible	= "jedec,lpddr3-timings";

		/* workaround: 'reg' shows max-freq */

		reg		= <800000000>;

		min-freq	= <100000000>;

		tRFC		= <65000>;

		tRRD		= <6000>;

		tRPab		= <12000>;

		tRPpb		= <12000>;

		tRCD		= <10000>;

		tRC		= <33750>;

		tRAS		= <23000>;

		tWTR		= <3750>;

		tWR		= <7500>;

		tRTP		= <3750>;

		tW2W-C2C	= <0>;

		tR2R-C2C	= <0>;

		tFAW		= <25000>;

		tXSR		= <70000>;

		tXP		= <3750>;

		tCKE		= <3750>;

		tCKESR		= <3750>;

		tMRD		= <7000>;

	};

}

Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml

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@@ -51,8 +51,7 @@ properties: 
    $ref: '/schemas/types.yaml#/definitions/phandle'

    description: |

      phandle of the connected DRAM memory device. For more information please

      refer to documentation file:

      Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt

      refer to jedec,lpddr3.yaml.



  operating-points-v2: true