dt-bindings: memory: lpddr3-timings: convert to dtschema

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPDDR3 SDRAM AC timing parameters for a given speed-bin

maintainers:

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

properties:

  compatible:

    const: jedec,lpddr3-timings

  reg:

    maxItems: 1

    description: |

      Maximum DDR clock frequency for the speed-bin, in Hz.

  min-freq:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Minimum DDR clock frequency for the speed-bin, in Hz.

  tCKE:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.

  tCKESR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      CKE minimum pulse width during SELF REFRESH (low pulse width during

      SELF REFRESH) in pico seconds.

  tFAW:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Four-bank activate window in pico seconds.

  tMRD:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Mode register set command delay in pico seconds.

  tR2R-C2C:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Additional READ-to-READ delay in chip-to-chip cases in pico seconds.

  tRAS:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Row active time in pico seconds.

  tRC:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      ACTIVATE-to-ACTIVATE command period in pico seconds.

  tRCD:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      RAS-to-CAS delay in pico seconds.

  tRFC:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Refresh Cycle time in pico seconds.

  tRPab:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Row precharge time (all banks) in pico seconds.

  tRPpb:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Row precharge time (single banks) in pico seconds.

  tRRD:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Active bank A to active bank B in pico seconds.

  tRTP:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Internal READ to PRECHARGE command delay in pico seconds.

  tW2W-C2C:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.

  tWR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      WRITE recovery time in pico seconds.

  tWTR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Internal WRITE-to-READ command delay in pico seconds.

  tXP:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Exit power-down to next valid command delay in pico seconds.

  tXSR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      SELF REFRESH exit to next valid command delay in pico seconds.

required:

  - compatible

  - min-freq

  - reg

additionalProperties: false

examples:

  - |

    lpddr3 {

        #address-cells = <1>;

        #size-cells = <0>;

        timings@800000000 {

            compatible = "jedec,lpddr3-timings";

            reg = <800000000>;

            min-freq = <100000000>;

            tCKE = <3750>;

            tCKESR = <3750>;

            tFAW = <25000>;

            tMRD = <7000>;

            tR2R-C2C = <0>;

            tRAS = <23000>;

            tRC = <33750>;

            tRCD = <10000>;

            tRFC = <65000>;

            tRPab = <12000>;

            tRPpb = <12000>;

            tRRD = <6000>;

            tRTP = <3750>;

            tW2W-C2C = <0>;

            tWR = <7500>;

            tWTR = <3750>;

            tXP = <3750>;

            tXSR = <70000>;

        };

    };

* AC timing parameters of LPDDR3 memories for a given speed-bin.

The structures are based on LPDDR2 and extended where needed.

Required properties:

- compatible : Should be "jedec,lpddr3-timings"

- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>

- reg : maximum DDR clock frequency for the speed-bin. Type is <u32>

Optional properties:

The following properties represent AC timing parameters from the memory

data-sheet of the device for a given speed-bin. All these properties are

of type <u32> and the default unit is ps (pico seconds).

- tRFC

- tRRD

- tRPab

- tRPpb

- tRCD

- tRC

- tRAS

- tWTR

- tWR

- tRTP

- tW2W-C2C

- tR2R-C2C

- tFAW

- tXSR

- tXP

- tCKE

- tCKESR

- tMRD

Example:

timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {

	compatible	= "jedec,lpddr3-timings";

	reg		= <800000000>; /* workaround: it shows max-freq */

	min-freq	= <100000000>;

	tRFC		= <65000>;

	tRRD		= <6000>;

	tRPab		= <12000>;

	tRPpb		= <12000>;

	tRCD		= <10000>;

	tRC		= <33750>;

	tRAS		= <23000>;

	tWTR		= <3750>;

	tWR		= <7500>;

	tRTP		= <3750>;

	tW2W-C2C	= <0>;

	tR2R-C2C	= <0>;

	tFAW		= <25000>;

	tXSR		= <70000>;

	tXP		= <3750>;

	tCKE		= <3750>;

	tCKESR		= <3750>;

	tMRD		= <7000>;

};