Unverified Commit 28e0377c authored by Mark Brown's avatar Mark Brown
Browse files

spi: mchp-pci1xxxx: Fix minor bugs in spi-pci1xxxx 

Merge series from Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>:

This patch series fixes the following bugs in spi-pci1xxxx driver:
1. Length of SPI transactions is improper
2. SPI transactions fail after suspend and resume
3. Incorrect implementation of pci1xxxx_spi_set_cs API
parents 4084c8ca 45d2af82

drivers/spi/spi-pci1xxxx.c

+7 −13
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ 
#define VENDOR_ID_MCHP 0x1055



#define SPI_SUSPEND_CONFIG 0x101

#define SPI_RESUME_CONFIG 0x303

#define SPI_RESUME_CONFIG 0x203



struct pci1xxxx_spi_internal {

	u8 hw_inst;
@@ -114,17 +114,14 @@ static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable) 


	/* Set the DEV_SEL bits of the SPI_MST_CTL_REG */

	regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));

	if (enable) {

	if (!enable) {

		regval |= SPI_FORCE_CE;

		regval &= ~SPI_MST_CTL_DEVSEL_MASK;

		regval |= (spi_get_chipselect(spi, 0) << 25);

		writel(regval,

		       par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));

	} else {

		regval &= ~(spi_get_chipselect(spi, 0) << 25);

		writel(regval,

		       par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));



		regval &= ~SPI_FORCE_CE;

	}

	writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));

}



static u8 pci1xxxx_get_clock_div(u32 hz)
@@ -199,8 +196,9 @@ static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr, 
			else

				regval &= ~SPI_MST_CTL_MODE_SEL;



			regval |= ((clkdiv << 5) | SPI_FORCE_CE | (len << 8));

			regval |= (clkdiv << 5);

			regval &= ~SPI_MST_CTL_CMD_LEN_MASK;

			regval |= (len << 8);

			writel(regval, par->reg_base +

			       SPI_MST_CTL_REG_OFFSET(p->hw_inst));

			regval = readl(par->reg_base +
@@ -222,10 +220,6 @@ static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr, 
			}

		}

	}



	regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));

	regval &= ~SPI_FORCE_CE;

	writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));

	p->spi_xfer_in_progress = false;



	return 0;