Commit 284f6dcb authored by Sam Protsenko's avatar Sam Protsenko Committed by Krzysztof Kozlowski
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dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks 



Add main gate clocks for controlling AUD and HSI CMUs:
  - gout_aud_cmu_aud_pclk
  - gout_hsi_cmu_hsi_pclk

While at it, add missing PPMU (Performance Profiling Monitor Unit)
clocks for CMU_HSI.

Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223042133.26551-3-semen.protsenko@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 521568cf

include/dt-bindings/clock/exynos850.h

+6 −2
Original line number Diff line number Diff line
@@ -178,7 +178,8 @@ 
#define IOCLK_AUDIOCDCLK5		58

#define IOCLK_AUDIOCDCLK6		59

#define TICK_USB			60

#define AUD_NR_CLK			61

#define CLK_GOUT_AUD_CMU_AUD_PCLK	61

#define AUD_NR_CLK			62



/* CMU_CMGP */

#define CLK_RCO_CMGP			1
@@ -227,7 +228,10 @@ 
#define CLK_GOUT_MMC_CARD_ACLK		11

#define CLK_GOUT_MMC_CARD_SDCLKIN	12

#define CLK_GOUT_SYSREG_HSI_PCLK	13

#define HSI_NR_CLK			14

#define CLK_GOUT_HSI_PPMU_ACLK		14

#define CLK_GOUT_HSI_PPMU_PCLK		15

#define CLK_GOUT_HSI_CMU_HSI_PCLK	16

#define HSI_NR_CLK			17



/* CMU_IS */

#define CLK_MOUT_IS_BUS_USER		1