Commit 270bbc72 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-doc', 'clk-renesas', 'clk-at91', 'clk-cleanup' and 'clk-debugfs' into clk-next 

* clk-doc:
  clk: Gemini: fix struct name in kernel-doc
  clk: zynq: pll: Fix kernel-doc warnings
  clk: imx: pllv1: fix kernel-doc notation for struct clk_pllv1

* clk-renesas: (31 commits)
  clk: renesas: r9a07g044: Add GPU clock and reset entries
  clk: renesas: r9a07g044: Add mux and divider for G clock
  clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
  clk: renesas: cpg-mssr: Add support for R-Car S4-8
  clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver
  dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
  dt-bindings: power: Add r8a779f0 SYSC power domain definitions
  clk: renesas: r9a07g044: Add TSU clock and reset entry
  mmc: renesas_sdhi: Simplify an expression
  mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock
  dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0
  clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()
  clk: renesas: cpg-mssr: Check return value of pm_genpd_init()
  clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()
  clk: renesas: rzg2l: Check return value of pm_genpd_init()
  clk: renesas: r9a07g044: Add RSPI clock and reset entries
  clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
  clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
  mmc: renesas_sdhi: Parse DT for SDnH
  mmc: renesas_sdhi: Use dev_err_probe when getting clock fails
  ...

* clk-at91:
  clk: lan966x: Extend lan966x clock driver for clock gating support
  dt-bindings: clock: lan966x: Extend includes with clock gates
  dt-bindings: clock: lan966x: Extend for clock gate support
  clk: gate: Add devm_clk_hw_register_gate()
  clk: lan966x: Add lan966x SoC clock driver
  dt-bindings: clock: lan966x: Add LAN966X Clock Controller
  dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs

* clk-cleanup:
  clk: stm32mp1: remove redundant assignment to pointer data
  clk: __clk_core_init() never takes NULL
  clk: clk_core_get() can also return NULL
  clk/ti/adpll: Make const pointer error a static const array

* clk-debugfs:
  clk: Enable/Disable runtime PM for clk_summary
  clk: Emit a stern warning with writable debugfs enabled
  clk: Add write operation for clk_parent debugfs node
parents ecb64bbf a5ce1d51 8f6b28c5 d66e4c98 1bb294a7

Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml

0 → 100644
+60 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip LAN966X Generic Clock Controller



maintainers:

  - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>



description: |

  The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,

  ddr_clk and sys_clk. This clock controller generates and supplies

  clock to various peripherals within the SoC.



properties:

  compatible:

    const: microchip,lan966x-gck



  reg:

    minItems: 1

    items:

      - description: Generic clock registers

      - description: Optional gate clock registers



  clocks:

    items:

      - description: CPU clock source

      - description: DDR clock source

      - description: System clock source



  clock-names:

    items:

      - const: cpu

      - const: ddr

      - const: sys



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clks: clock-controller@e00c00a8 {

        compatible = "microchip,lan966x-gck";

        #clock-cells = <1>;

        clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;

        clock-names = "cpu", "ddr", "sys";

        reg = <0xe00c00a8 0x38>;

    };

...

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

+1 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ properties: 
      - renesas,r8a77990-cpg-mssr # R-Car E3

      - renesas,r8a77995-cpg-mssr # R-Car D3

      - renesas,r8a779a0-cpg-mssr # R-Car V3U

      - renesas,r8a779f0-cpg-mssr # R-Car S4-8



  reg:

    maxItems: 1

drivers/clk/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -221,6 +221,13 @@ config COMMON_CLK_GEMINI 
	  This driver supports the SoC clocks on the Cortina Systems Gemini

	  platform, also known as SL3516 or CS3516.



config COMMON_CLK_LAN966X

	bool "Generic Clock Controller driver for LAN966X SoC"

	help

	  This driver provides support for Generic Clock Controller(GCK) on

	  LAN966X SoC. GCK generates and supplies clock to various peripherals

	  within the SoC.



config COMMON_CLK_ASPEED

	bool "Clock driver for Aspeed BMC SoCs"

	depends on ARCH_ASPEED || COMPILE_TEST

drivers/clk/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o 
obj-$(CONFIG_CLK_HSDK)			+= clk-hsdk-pll.o

obj-$(CONFIG_COMMON_CLK_K210)		+= clk-k210.o

obj-$(CONFIG_LMK04832)			+= clk-lmk04832.o

obj-$(CONFIG_COMMON_CLK_LAN966X)	+= clk-lan966x.o

obj-$(CONFIG_COMMON_CLK_LOCHNAGAR)	+= clk-lochnagar.o

obj-$(CONFIG_COMMON_CLK_MAX77686)	+= clk-max77686.o

obj-$(CONFIG_COMMON_CLK_MAX9485)	+= clk-max9485.o

drivers/clk/clk-gate.c

+35 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
 */



#include <linux/clk-provider.h>

#include <linux/device.h>

#include <linux/module.h>

#include <linux/slab.h>

#include <linux/io.h>
@@ -222,3 +223,37 @@ void clk_hw_unregister_gate(struct clk_hw *hw) 
	kfree(gate);

}

EXPORT_SYMBOL_GPL(clk_hw_unregister_gate);



static void devm_clk_hw_release_gate(struct device *dev, void *res)

{

	clk_hw_unregister_gate(*(struct clk_hw **)res);

}



struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,

		struct device_node *np, const char *name,

		const char *parent_name, const struct clk_hw *parent_hw,

		const struct clk_parent_data *parent_data,

		unsigned long flags,

		void __iomem *reg, u8 bit_idx,

		u8 clk_gate_flags, spinlock_t *lock)

{

	struct clk_hw **ptr, *hw;



	ptr = devres_alloc(devm_clk_hw_release_gate, sizeof(*ptr), GFP_KERNEL);

	if (!ptr)

		return ERR_PTR(-ENOMEM);



	hw = __clk_hw_register_gate(dev, np, name, parent_name, parent_hw,

				    parent_data, flags, reg, bit_idx,

				    clk_gate_flags, lock);



	if (!IS_ERR(hw)) {

		*ptr = hw;

		devres_add(dev, ptr);

	} else {

		devres_free(ptr);

	}



	return hw;

}

EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate);