Commit a5ce1d51 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v5.17-tag2' of... 

Merge tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
 - Add GPU clock and resets on Renesas RZ/G2L
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a07g044: Add GPU clock and reset entries
  clk: renesas: r9a07g044: Add mux and divider for G clock
  clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
  clk: renesas: cpg-mssr: Add support for R-Car S4-8
  clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver
  dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
  dt-bindings: power: Add r8a779f0 SYSC power domain definitions
parents 1dfeb03e f0b62b0b

drivers/clk/renesas/Kconfig

+11 −2
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ config CLK_RENESAS 
	select CLK_R8A77990 if ARCH_R8A77990

	select CLK_R8A77995 if ARCH_R8A77995

	select CLK_R8A779A0 if ARCH_R8A779A0

	select CLK_R8A779F0 if ARCH_R8A779F0

	select CLK_R9A06G032 if ARCH_R9A06G032

	select CLK_R9A07G044 if ARCH_R9A07G044

	select CLK_SH73A0 if ARCH_SH73A0
@@ -149,8 +150,11 @@ config CLK_R8A77995 


config CLK_R8A779A0

	bool "R-Car V3U clock support" if COMPILE_TEST

	select CLK_RCAR_CPG_LIB

	select CLK_RENESAS_CPG_MSSR

	select CLK_RCAR_GEN4_CPG



config CLK_R8A779F0

	bool "R-Car S4-8 clock support" if COMPILE_TEST

	select CLK_RCAR_GEN4_CPG



config CLK_R9A06G032

	bool "RZ/N1D clock support" if COMPILE_TEST
@@ -178,6 +182,11 @@ config CLK_RCAR_GEN3_CPG 
	select CLK_RCAR_CPG_LIB

	select CLK_RENESAS_CPG_MSSR



config CLK_RCAR_GEN4_CPG

	bool "R-Car Gen4 clock support" if COMPILE_TEST

	select CLK_RCAR_CPG_LIB

	select CLK_RENESAS_CPG_MSSR



config CLK_RCAR_USB2_CLOCK_SEL

	bool "Renesas R-Car USB2 clock selector support"

	depends on ARCH_RENESAS || COMPILE_TEST

drivers/clk/renesas/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o 
obj-$(CONFIG_CLK_R8A77990)		+= r8a77990-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77995)		+= r8a77995-cpg-mssr.o

obj-$(CONFIG_CLK_R8A779A0)		+= r8a779a0-cpg-mssr.o

obj-$(CONFIG_CLK_R8A779F0)		+= r8a779f0-cpg-mssr.o

obj-$(CONFIG_CLK_R9A06G032)		+= r9a06g032-clocks.o

obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
@@ -36,6 +37,7 @@ obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o 
obj-$(CONFIG_CLK_RCAR_CPG_LIB)		+= rcar-cpg-lib.o

obj-$(CONFIG_CLK_RCAR_GEN2_CPG)		+= rcar-gen2-cpg.o

obj-$(CONFIG_CLK_RCAR_GEN3_CPG)		+= rcar-gen3-cpg.o

obj-$(CONFIG_CLK_RCAR_GEN4_CPG)		+= rcar-gen4-cpg.o

obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL)	+= rcar-usb2-clock-sel.o

obj-$(CONFIG_CLK_RZG2L)			+= rzg2l-cpg.o

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+26 −324
Original line number Diff line number Diff line
@@ -10,47 +10,19 @@ 
 * Copyright (C) 2015 Renesas Electronics Corp.

 */



#include <linux/bug.h>

#include <linux/bitfield.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/device.h>

#include <linux/err.h>

#include <linux/init.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/pm.h>

#include <linux/slab.h>

#include <linux/soc/renesas/rcar-rst.h>



#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>



#include "rcar-cpg-lib.h"

#include "renesas-cpg-mssr.h"



enum rcar_r8a779a0_clk_types {

	CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,

	CLK_TYPE_R8A779A0_PLL1,

	CLK_TYPE_R8A779A0_PLL2X_3X,	/* PLL[23][01] */

	CLK_TYPE_R8A779A0_PLL5,

	CLK_TYPE_R8A779A0_Z,

	CLK_TYPE_R8A779A0_SDH,

	CLK_TYPE_R8A779A0_SD,

	CLK_TYPE_R8A779A0_MDSEL,	/* Select parent/divider using mode pin */

	CLK_TYPE_R8A779A0_OSC,	/* OSC EXTAL predivider and fixed divider */

	CLK_TYPE_R8A779A0_RPCSRC,

	CLK_TYPE_R8A779A0_RPC,

	CLK_TYPE_R8A779A0_RPCD2,

};



struct rcar_r8a779a0_cpg_pll_config {

	u8 extal_div;

	u8 pll1_mult;

	u8 pll1_div;

	u8 pll5_mult;

	u8 pll5_div;

	u8 osc_prediv;

};

#include "rcar-gen4-cpg.h"



enum clk_ids {

	/* Core Clock Outputs exported to DT */
@@ -86,36 +58,18 @@ enum clk_ids { 
};



#define DEF_PLL(_name, _id, _offset)	\

	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \

		 .offset = _offset)



#define DEF_Z(_name, _id, _parent, _div, _offset)	\

	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_Z, _parent, .div = _div,	\

	DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \

		 .offset = _offset)



#define DEF_SDH(_name, _id, _parent, _offset)   \

	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SDH, _parent, .offset = _offset)



#define DEF_SD(_name, _id, _parent, _offset)   \

	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)



#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \

	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL,	\

		 (_parent0) << 16 | (_parent1),		\

		 .div = (_div0) << 16 | (_div1), .offset = _md)



#define DEF_OSC(_name, _id, _parent, _div)		\

	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)



static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {

	/* External Clock Inputs */

	DEF_INPUT("extal",  CLK_EXTAL),

	DEF_INPUT("extalr", CLK_EXTALR),



	/* Internal Core Clocks */

	DEF_BASE(".main", CLK_MAIN,	CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),

	DEF_BASE(".pll1", CLK_PLL1,	CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),

	DEF_BASE(".pll5", CLK_PLL5,	CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),

	DEF_BASE(".main", CLK_MAIN,	CLK_TYPE_GEN4_MAIN, CLK_EXTAL),

	DEF_BASE(".pll1", CLK_PLL1,	CLK_TYPE_GEN4_PLL1, CLK_MAIN),

	DEF_BASE(".pll5", CLK_PLL5,	CLK_TYPE_GEN4_PLL5, CLK_MAIN),

	DEF_PLL(".pll20", CLK_PLL20,	0x0834),

	DEF_PLL(".pll21", CLK_PLL21,	0x0838),

	DEF_PLL(".pll30", CLK_PLL30,	0x083c),
@@ -132,14 +86,14 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_FIXED(".s3",		CLK_S3,		CLK_PLL1_DIV2,	4, 1),

	DEF_FIXED(".sdsrc",		CLK_SDSRC,	CLK_PLL5_DIV4,	1, 1),

	DEF_RATE(".oco",		CLK_OCO,	32768),

	DEF_BASE(".rpcsrc",	 CLK_RPCSRC,	   CLK_TYPE_R8A779A0_RPCSRC, CLK_PLL5),

	DEF_BASE("rpc",		 R8A779A0_CLK_RPC, CLK_TYPE_R8A779A0_RPC, CLK_RPCSRC),

	DEF_BASE("rpcd2",	 R8A779A0_CLK_RPCD2, CLK_TYPE_R8A779A0_RPCD2,

	DEF_BASE(".rpcsrc",	 CLK_RPCSRC,	   CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),

	DEF_BASE("rpc",		 R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),

	DEF_BASE("rpcd2",	 R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,

		 R8A779A0_CLK_RPC),



	/* Core Clock Outputs */

	DEF_Z("z0",		R8A779A0_CLK_Z0,	CLK_PLL20,	2, 0),

	DEF_Z("z1",		R8A779A0_CLK_Z1,	CLK_PLL21,	2, 8),

	DEF_GEN4_Z("z0",	R8A779A0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL20,	2, 0),

	DEF_GEN4_Z("z1",	R8A779A0_CLK_Z1,	CLK_TYPE_GEN4_Z,	CLK_PLL21,	2, 8),

	DEF_FIXED("zx",		R8A779A0_CLK_ZX,	CLK_PLL20_DIV2,	2, 1),

	DEF_FIXED("s1d1",	R8A779A0_CLK_S1D1,	CLK_S1,		1, 1),

	DEF_FIXED("s1d2",	R8A779A0_CLK_S1D2,	CLK_S1,		2, 1),
@@ -163,16 +117,16 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_FIXED("cp",		R8A779A0_CLK_CP,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cl16mck",	R8A779A0_CLK_CL16MCK,	CLK_PLL1_DIV2,	64, 1),



	DEF_SDH("sdh0",		R8A779A0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_SD("sd0",		R8A779A0_CLK_SD0,	R8A779A0_CLK_SD0H, 0x870),

	DEF_GEN4_SDH("sdh0",	R8A779A0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SD("sd0",	R8A779A0_CLK_SD0,	R8A779A0_CLK_SD0H, 0x870),



	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),

	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),

	DEF_DIV6P1("csi0",	R8A779A0_CLK_CSI0,	CLK_PLL5_DIV4,	0x880),

	DEF_DIV6P1("dsi",	R8A779A0_CLK_DSI,	CLK_PLL5_DIV4,	0x884),



	DEF_OSC("osc",		R8A779A0_CLK_OSC,	CLK_EXTAL,	8),

	DEF_MDSEL("r",		R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),

	DEF_GEN4_OSC("osc",	R8A779A0_CLK_OSC,	CLK_EXTAL,	8),

	DEF_GEN4_MDSEL("r",	R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),

};



static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
@@ -276,258 +230,6 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("vspx3",	1031,	R8A779A0_CLK_S1D1),

};



static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata;

static unsigned int cpg_clk_extalr __initdata;

static u32 cpg_mode __initdata;



/*

 * Z0 Clock & Z1 Clock

 */

#define CPG_FRQCRB			0x00000804

#define CPG_FRQCRB_KICK			BIT(31)

#define CPG_FRQCRC			0x00000808



struct cpg_z_clk {

	struct clk_hw hw;

	void __iomem *reg;

	void __iomem *kick_reg;

	unsigned long max_rate;		/* Maximum rate for normal mode */

	unsigned int fixed_div;

	u32 mask;

};



#define to_z_clk(_hw)	container_of(_hw, struct cpg_z_clk, hw)



static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,

					   unsigned long parent_rate)

{

	struct cpg_z_clk *zclk = to_z_clk(hw);

	unsigned int mult;

	u32 val;



	val = readl(zclk->reg) & zclk->mask;

	mult = 32 - (val >> __ffs(zclk->mask));



	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,

				     32 * zclk->fixed_div);

}



static int cpg_z_clk_determine_rate(struct clk_hw *hw,

				    struct clk_rate_request *req)

{

	struct cpg_z_clk *zclk = to_z_clk(hw);

	unsigned int min_mult, max_mult, mult;

	unsigned long rate, prate;



	rate = min(req->rate, req->max_rate);

	if (rate <= zclk->max_rate) {

		/* Set parent rate to initial value for normal modes */

		prate = zclk->max_rate;

	} else {

		/* Set increased parent rate for boost modes */

		prate = rate;

	}

	req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),

						  prate * zclk->fixed_div);



	prate = req->best_parent_rate / zclk->fixed_div;

	min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);

	max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);

	if (max_mult < min_mult)

		return -EINVAL;



	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);

	mult = clamp(mult, min_mult, max_mult);



	req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);

	return 0;

}



static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,

			      unsigned long parent_rate)

{

	struct cpg_z_clk *zclk = to_z_clk(hw);

	unsigned int mult;

	unsigned int i;



	mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,

				       parent_rate);

	mult = clamp(mult, 1U, 32U);



	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)

		return -EBUSY;



	cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));



	/*

	 * Set KICK bit in FRQCRB to update hardware setting and wait for

	 * clock change completion.

	 */

	cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);



	/*

	 * Note: There is no HW information about the worst case latency.

	 *

	 * Using experimental measurements, it seems that no more than

	 * ~10 iterations are needed, independently of the CPU rate.

	 * Since this value might be dependent on external xtal rate, pll1

	 * rate or even the other emulation clocks rate, use 1000 as a

	 * "super" safe value.

	 */

	for (i = 1000; i; i--) {

		if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))

			return 0;



		cpu_relax();

	}



	return -ETIMEDOUT;

}



static const struct clk_ops cpg_z_clk_ops = {

	.recalc_rate = cpg_z_clk_recalc_rate,

	.determine_rate = cpg_z_clk_determine_rate,

	.set_rate = cpg_z_clk_set_rate,

};



static struct clk * __init cpg_z_clk_register(const char *name,

					      const char *parent_name,

					      void __iomem *reg,

					      unsigned int div,

					      unsigned int offset)

{

	struct clk_init_data init = {};

	struct cpg_z_clk *zclk;

	struct clk *clk;



	zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);

	if (!zclk)

		return ERR_PTR(-ENOMEM);



	init.name = name;

	init.ops = &cpg_z_clk_ops;

	init.flags = CLK_SET_RATE_PARENT;

	init.parent_names = &parent_name;

	init.num_parents = 1;



	zclk->reg = reg + CPG_FRQCRC;

	zclk->kick_reg = reg + CPG_FRQCRB;

	zclk->hw.init = &init;

	zclk->mask = GENMASK(offset + 4, offset);

	zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */



	clk = clk_register(NULL, &zclk->hw);

	if (IS_ERR(clk)) {

		kfree(zclk);

		return clk;

	}



	zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /

			 zclk->fixed_div;

	return clk;

}



/*

 * RPC Clocks

 */

#define CPG_RPCCKCR 0x874



static const struct clk_div_table cpg_rpcsrc_div_table[] = {

	{ 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },

};



static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,

	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,

	struct clk **clks, void __iomem *base,

	struct raw_notifier_head *notifiers)

{

	const struct clk *parent;

	unsigned int mult = 1;

	unsigned int div = 1;

	u32 value;



	parent = clks[core->parent & 0xffff];	/* some types use high bits */

	if (IS_ERR(parent))

		return ERR_CAST(parent);



	switch (core->type) {

	case CLK_TYPE_R8A779A0_MAIN:

		div = cpg_pll_config->extal_div;

		break;



	case CLK_TYPE_R8A779A0_PLL1:

		mult = cpg_pll_config->pll1_mult;

		div = cpg_pll_config->pll1_div;

		break;



	case CLK_TYPE_R8A779A0_PLL2X_3X:

		value = readl(base + core->offset);

		mult = (((value >> 24) & 0x7f) + 1) * 2;

		break;



	case CLK_TYPE_R8A779A0_PLL5:

		mult = cpg_pll_config->pll5_mult;

		div = cpg_pll_config->pll5_div;

		break;



	case CLK_TYPE_R8A779A0_Z:

		return cpg_z_clk_register(core->name, __clk_get_name(parent),

					  base, core->div, core->offset);



	case CLK_TYPE_R8A779A0_SDH:

		return cpg_sdh_clk_register(core->name, base + core->offset,

					   __clk_get_name(parent), notifiers);



	case CLK_TYPE_R8A779A0_SD:

		return cpg_sd_clk_register(core->name, base + core->offset,

					   __clk_get_name(parent));



	case CLK_TYPE_R8A779A0_MDSEL:

		/*

		 * Clock selectable between two parents and two fixed dividers

		 * using a mode pin

		 */

		if (cpg_mode & BIT(core->offset)) {

			div = core->div & 0xffff;

		} else {

			parent = clks[core->parent >> 16];

			if (IS_ERR(parent))

				return ERR_CAST(parent);

			div = core->div >> 16;

		}

		mult = 1;

		break;



	case CLK_TYPE_R8A779A0_OSC:

		/*

		 * Clock combining OSC EXTAL predivider and a fixed divider

		 */

		div = cpg_pll_config->osc_prediv * core->div;

		break;



	case CLK_TYPE_R8A779A0_RPCSRC:

		return clk_register_divider_table(NULL, core->name,

						  __clk_get_name(parent), 0,

						  base + CPG_RPCCKCR, 3, 2, 0,

						  cpg_rpcsrc_div_table,

						  &cpg_lock);



	case CLK_TYPE_R8A779A0_RPC:

		return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,

					    __clk_get_name(parent), notifiers);



	case CLK_TYPE_R8A779A0_RPCD2:

		return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,

					      __clk_get_name(parent));



	default:

		return ERR_PTR(-EINVAL);

	}



	return clk_register_fixed_factor(NULL, core->name,

					 __clk_get_name(parent), 0, mult, div);

}



static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {

	MOD_CLK_ID(907),	/* RWDT */

};
@@ -546,17 +248,19 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { 
 */

#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \

					 (((md) & BIT(13)) >> 13))



static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = {

	/* EXTAL div	PLL1 mult/div	PLL5 mult/div	OSC prediv */

	{ 1,		128,	1,	192,	1,	16,	},

	{ 1,		106,	1,	160,	1,	19,	},

	{ 0,		0,	0,	0,	0,	0,	},

	{ 2,		128,	1,	192,	1,	32,	},

static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {

	/* EXTAL div	PLL1 mult/div	PLL2 mult/div	PLL3 mult/div	PLL5 mult/div	PLL6 mult/div	OSC prediv */

	{ 1,		128,	1,	0,	0,	0,	0,	192,	1,	0,	0,	16,	},

	{ 1,		106,	1,	0,	0,	0,	0,	160,	1,	0,	0,	19,	},

	{ 0,		0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	},

	{ 2,		128,	1,	0,	0,	0,	0,	192,	1,	0,	0,	32,	},

};





static int __init r8a779a0_cpg_mssr_init(struct device *dev)

{

	const struct rcar_gen4_cpg_pll_config *cpg_pll_config;

	u32 cpg_mode;

	int error;



	error = rcar_rst_read_mode_pins(&cpg_mode);
@@ -564,10 +268,8 @@ static int __init r8a779a0_cpg_mssr_init(struct device *dev) 
		return error;



	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];

	cpg_clk_extalr = CLK_EXTALR;

	spin_lock_init(&cpg_lock);



	return 0;

	return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);

}



const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
@@ -588,7 +290,7 @@ const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { 


	/* Callbacks */

	.init = r8a779a0_cpg_mssr_init,

	.cpg_clk_register = rcar_r8a779a0_cpg_clk_register,

	.cpg_clk_register = rcar_gen4_cpg_clk_register,



	.reg_layout = CLK_REG_LAYOUT_RCAR_V3U,

	.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,

};

drivers/clk/renesas/r8a779f0-cpg-mssr.c

0 → 100644
+183 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset

 *

 * Copyright (C) 2021 Renesas Electronics Corp.

 *

 * Based on r8a779a0-cpg-mssr.c

 */



#include <linux/bitfield.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/device.h>

#include <linux/err.h>

#include <linux/kernel.h>

#include <linux/soc/renesas/rcar-rst.h>



#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>



#include "renesas-cpg-mssr.h"

#include "rcar-gen4-cpg.h"



enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R8A779F0_CLK_R,



	/* External Input Clocks */

	CLK_EXTAL,

	CLK_EXTALR,



	/* Internal Core Clocks */

	CLK_MAIN,

	CLK_PLL1,

	CLK_PLL2,

	CLK_PLL3,

	CLK_PLL5,

	CLK_PLL6,

	CLK_PLL1_DIV2,

	CLK_PLL2_DIV2,

	CLK_PLL3_DIV2,

	CLK_PLL5_DIV2,

	CLK_PLL5_DIV4,

	CLK_PLL6_DIV2,

	CLK_S0,

	CLK_SDSRC,

	CLK_RPCSRC,

	CLK_OCO,



	/* Module Clocks */

	MOD_CLK_BASE

};



static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {

	/* External Clock Inputs */

	DEF_INPUT("extal",	CLK_EXTAL),

	DEF_INPUT("extalr",	CLK_EXTALR),



	/* Internal Core Clocks */

	DEF_BASE(".main", CLK_MAIN,	CLK_TYPE_GEN4_MAIN, CLK_EXTAL),

	DEF_BASE(".pll1", CLK_PLL1,	CLK_TYPE_GEN4_PLL1, CLK_MAIN),

	DEF_BASE(".pll2", CLK_PLL2,	CLK_TYPE_GEN4_PLL2, CLK_MAIN),

	DEF_BASE(".pll3", CLK_PLL3,	CLK_TYPE_GEN4_PLL3, CLK_MAIN),

	DEF_BASE(".pll5", CLK_PLL5,	CLK_TYPE_GEN4_PLL5, CLK_MAIN),

	DEF_BASE(".pll6", CLK_PLL6,	CLK_TYPE_GEN4_PLL6, CLK_MAIN),



	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),

	DEF_FIXED(".pll2_div2",	CLK_PLL2_DIV2,	CLK_PLL2,	2, 1),

	DEF_FIXED(".pll3_div2",	CLK_PLL3_DIV2,	CLK_PLL3,	2, 1),

	DEF_FIXED(".pll5_div2",	CLK_PLL5_DIV2,	CLK_PLL5,	2, 1),

	DEF_FIXED(".pll5_div4",	CLK_PLL5_DIV4,	CLK_PLL5_DIV2,	2, 1),

	DEF_FIXED(".pll6_div2",	CLK_PLL6_DIV2,	CLK_PLL6,	2, 1),

	DEF_FIXED(".s0",	CLK_S0,		CLK_PLL1_DIV2,	2, 1),

	DEF_BASE(".sdsrc",	CLK_SDSRC,	CLK_TYPE_GEN4_SDSRC, CLK_PLL5),

	DEF_RATE(".oco",	CLK_OCO,	32768),



	DEF_BASE(".rpcsrc",	CLK_RPCSRC,		CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),

	DEF_BASE(".rpc",	R8A779F0_CLK_RPC,	CLK_TYPE_GEN4_RPC, CLK_RPCSRC),

	DEF_BASE("rpcd2",	R8A779F0_CLK_RPCD2,	CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),



	/* Core Clock Outputs */

	DEF_FIXED("s0d2",	R8A779F0_CLK_S0D2,	CLK_S0,		2, 1),

	DEF_FIXED("s0d3",	R8A779F0_CLK_S0D3,	CLK_S0,		3, 1),

	DEF_FIXED("s0d4",	R8A779F0_CLK_S0D4,	CLK_S0,		4, 1),

	DEF_FIXED("cl16m",	R8A779F0_CLK_CL16M,	CLK_S0,		48, 1),

	DEF_FIXED("s0d2_mm",	R8A779F0_CLK_S0D2_MM,	CLK_S0,		2, 1),

	DEF_FIXED("s0d3_mm",	R8A779F0_CLK_S0D3_MM,	CLK_S0,		3, 1),

	DEF_FIXED("s0d4_mm",	R8A779F0_CLK_S0D4_MM,	CLK_S0,		4, 1),

	DEF_FIXED("cl16m_mm",	R8A779F0_CLK_CL16M_MM,	CLK_S0,		48, 1),

	DEF_FIXED("s0d2_rt",	R8A779F0_CLK_S0D2_RT,	CLK_S0,		2, 1),

	DEF_FIXED("s0d3_rt",	R8A779F0_CLK_S0D3_RT,	CLK_S0,		3, 1),

	DEF_FIXED("s0d4_rt",	R8A779F0_CLK_S0D4_RT,	CLK_S0,		4, 1),

	DEF_FIXED("s0d6_rt",	R8A779F0_CLK_S0D6_RT,	CLK_S0,		6, 1),

	DEF_FIXED("cl16m_rt",	R8A779F0_CLK_CL16M_RT,	CLK_S0,		48, 1),

	DEF_FIXED("s0d3_per",	R8A779F0_CLK_S0D3_PER,	CLK_S0,		3, 1),

	DEF_FIXED("s0d6_per",	R8A779F0_CLK_S0D6_PER,	CLK_S0,		6, 1),

	DEF_FIXED("s0d12_per",	R8A779F0_CLK_S0D12_PER,	CLK_S0,		12, 1),

	DEF_FIXED("s0d24_per",	R8A779F0_CLK_S0D24_PER,	CLK_S0,		24, 1),

	DEF_FIXED("cl16m_per",	R8A779F0_CLK_CL16M_PER,	CLK_S0,		48, 1),

	DEF_FIXED("s0d2_hsc",	R8A779F0_CLK_S0D2_HSC,	CLK_S0,		2, 1),

	DEF_FIXED("s0d3_hsc",	R8A779F0_CLK_S0D3_HSC,	CLK_S0,		3, 1),

	DEF_FIXED("s0d4_hsc",	R8A779F0_CLK_S0D4_HSC,	CLK_S0,		4, 1),

	DEF_FIXED("s0d6_hsc",	R8A779F0_CLK_S0D6_HSC,	CLK_S0,		6, 1),

	DEF_FIXED("s0d12_hsc",	R8A779F0_CLK_S0D12_HSC,	CLK_S0,		12, 1),

	DEF_FIXED("cl16m_hsc",	R8A779F0_CLK_CL16M_HSC,	CLK_S0,		48, 1),

	DEF_FIXED("s0d2_cc",	R8A779F0_CLK_S0D2_CC,	CLK_S0,		2, 1),

	DEF_FIXED("rsw2",	R8A779F0_CLK_RSW2,	CLK_PLL5,	2, 1),

	DEF_FIXED("cbfusa",	R8A779F0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cpex",	R8A779F0_CLK_CPEX,	CLK_EXTAL,	2, 1),



	DEF_GEN4_SD("sd0",	R8A779F0_CLK_SD0,	CLK_SDSRC,	0x870),

	DEF_DIV6P1("mso",	R8A779F0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),



	DEF_GEN4_OSC("osc",	R8A779F0_CLK_OSC,	CLK_EXTAL,	8),

	DEF_GEN4_MDSEL("r",	R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),

};



static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {

	DEF_MOD("scif0",	702,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif1",	703,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif3",	704,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif4",	705,	R8A779F0_CLK_S0D12_PER),

};



/*

 * CPG Clock Data

 */

/*

 *   MD	 EXTAL		PLL1	PLL2	PLL3	PLL5	PLL6	OSC

 * 14 13 (MHz)

 * ----------------------------------------------------------------

 * 0  0	 16    / 1	x200	x150	x200	x200	x134	/15

 * 0  1	 20    / 1	x160	x120	x160	x160	x106	/19

 * 1  0	 Prohibited setting

 * 1  1	 40    / 2	x160	x120	x160	x160	x106	/38

 */

#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \

					 (((md) & BIT(13)) >> 13))



static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {

	/* EXTAL div	PLL1 mult/div	PLL2 mult/div	PLL3 mult/div	PLL5 mult/div	PLL6 mult/div	OSC prediv */

	{ 1,		200,	1,	150,	1,	200,	1,	200,	1,	134,	1,	15,	},

	{ 1,		160,	1,	120,	1,	160,	1,	160,	1,	106,	1,	19,	},

	{ 0,		0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	},

	{ 2,		160,	1,	120,	1,	160,	1,	160,	1,	106,	1,	38,	},

};



static int __init r8a779f0_cpg_mssr_init(struct device *dev)

{

	const struct rcar_gen4_cpg_pll_config *cpg_pll_config;

	u32 cpg_mode;

	int error;



	error = rcar_rst_read_mode_pins(&cpg_mode);

	if (error)

		return error;



	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];

	if (!cpg_pll_config->extal_div) {

		dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);

		return -EINVAL;

	}



	return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);

}



const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = {

	/* Core Clocks */

	.core_clks = r8a779f0_core_clks,

	.num_core_clks = ARRAY_SIZE(r8a779f0_core_clks),

	.last_dt_core_clk = LAST_DT_CORE_CLK,

	.num_total_core_clks = MOD_CLK_BASE,



	/* Module Clocks */

	.mod_clks = r8a779f0_mod_clks,

	.num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks),

	.num_hw_mod_clks = 28 * 32,



	/* Callbacks */

	.init = r8a779f0_cpg_mssr_init,

	.cpg_clk_register = rcar_gen4_cpg_clk_register,



	.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,

};

drivers/clk/renesas/r9a07g044-cpg.c

+17 −2
Original line number Diff line number Diff line
@@ -32,9 +32,9 @@ enum clk_ids { 
	CLK_PLL3_400,

	CLK_PLL3_533,

	CLK_PLL3_DIV2,

	CLK_PLL3_DIV2_2,

	CLK_PLL3_DIV2_4,

	CLK_PLL3_DIV2_4_2,

	CLK_PLL3_DIV4,

	CLK_SEL_PLL3_3,

	CLK_DIV_PLL3_C,

	CLK_PLL4,
@@ -50,6 +50,7 @@ enum clk_ids { 
	CLK_PLL2_SDHI_266,

	CLK_SD0_DIV4,

	CLK_SD1_DIV4,

	CLK_SEL_GPU2,



	/* Module Clocks */

	MOD_CLK_BASE,
@@ -77,6 +78,7 @@ static const struct clk_div_table dtable_1_32[] = { 
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };

static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };

static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };

static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };



static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {

	/* External Clock Inputs */
@@ -106,9 +108,9 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),



	DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),

	DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),

	DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),

	DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),

	DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),

	DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,

		sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),

	DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
@@ -116,6 +118,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 


	DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),

	DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),

	DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,

		sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),



	/* Core output clk */

	DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
@@ -141,6 +145,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
		   sel_shdi, ARRAY_SIZE(sel_shdi)),

	DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),

	DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),

	DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,

		CLK_DIVIDER_HIWORD_MASK),

};



static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
@@ -192,6 +198,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 
				0x554, 6),

	DEF_MOD("sdhi1_aclk",	R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,

				0x554, 7),

	DEF_MOD("gpu_clk",	R9A07G044_GPU_CLK, R9A07G044_CLK_G,

				0x558, 0),

	DEF_MOD("gpu_axi_clk",	R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,

				0x558, 1),

	DEF_MOD("gpu_ace_clk",	R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,

				0x558, 2),

	DEF_MOD("ssi0_pclk",	R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,

				0x570, 0),

	DEF_MOD("ssi0_sfr",	R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
@@ -279,6 +291,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_SPI_RST, 0x850, 0),

	DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),

	DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),

	DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),

	DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),

	DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),

	DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),

	DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),

	DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),