x86/fpu: Cache xfeature flags from CPUID

mainline inclusion
from mainline-v5.18-rc1
commit 6afbb58c
category: bugfix
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I73H0T
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6afbb58cc2251c1d83472ca3005638206e73b6b8



Intel-SIG: commit 6afbb58c x86/fpu: Cache xfeature flags from CPUID.

--------------------------------

In preparation for runtime calculation of XSAVE offsets cache the feature
flags for each XSTATE component during feature enumeration via CPUID(0xD).

EDX has two relevant bits:
    0	Supervisor component
    1	Feature storage must be 64 byte aligned

These bits are currently only evaluated during init, but the alignment bit
must be cached to make runtime calculation of XSAVE offsets efficient.

Cache the full EDX content and use it for the existing alignment and
supervisor checks.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220324134623.573656209@linutronix.de


Signed-off-by: Lin Wang <lin.x.wang@intel.com>