Commit 2680bea7 authored by José Roberto de Souza's avatar José Roberto de Souza Committed by Matt Roper
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drm/i915/display/adl_p: Implement Wa_22011320316 



Implementation details are in the HSD 22011320316, requiring CD clock
to be at least 307MHz to make DC states to work.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarClinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-19-matthew.d.roper@intel.com
parent a8a56da7

drivers/gpu/drm/i915/display/intel_cdclk.c

+20 −1
Original line number Diff line number Diff line
@@ -1253,6 +1253,21 @@ static const struct intel_cdclk_vals rkl_cdclk_table[] = { 
	{}

};



static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {

	{ .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },

	{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },

	{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },



	{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },

	{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },

	{ .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },



	{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },

	{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },

	{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },

	{}

};



static const struct intel_cdclk_vals adlp_cdclk_table[] = {

	{ .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },

	{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
@@ -2801,6 +2816,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;

		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;

		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;

		/* Wa_22011320316:adlp[a0] */

		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))

			dev_priv->cdclk.table = adlp_a_step_cdclk_table;

		else

			dev_priv->cdclk.table = adlp_cdclk_table;

	} else if (IS_ROCKETLAKE(dev_priv)) {

		dev_priv->display.set_cdclk = bxt_set_cdclk;